[coreboot] Patch set updated for coreboot: 81ce194 AMD agesa family15: PCI domain should scan bus from 0x18.0

Siyuan Wang (wangsiyuanbuaa@gmail.com) gerrit at coreboot.org
Sun Nov 4 09:08:05 CET 2012

Siyuan Wang (wangsiyuanbuaa at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1639


commit 81ce194670a80b75b49877ceb5d809c1a4d11eb4
Author: Siyuan Wang <wangsiyuanbuaa at gmail.com>
Date:   Sun Oct 28 18:06:40 2012 +0800

    AMD agesa family15: PCI domain should scan bus from 0x18.0
    There are 4 mainboards using agesa family15 code:
    Supermicro h8scm and h8qgi, Tyan s8226 and AMD dinar.
    All of these boards' PCI domain starts from 0x18.0. Take h8scm as
    an example, PCI devices from 0.0 to 0x14.5 is under 0x18.0.
    Now, the PCI domain's scan bus function stats from 0.0. This would
    result to the PCI devices be scanned twice. Because when the function
    run to device 18.0, it would scan from 0.0 again.
    This issue would result to 2 problems:
    1) PCI device may be assigned two different PCI address.
       If this happenned on VGA device, coreboot maybe not load
       vga bios correctly.
    2) coreboot initializes rd890's IO APIC twice.
    So this patch scans from 0x18.0 and could resolve the problems above.
    Change-Id: I90fbdf695413fd24c7a5e3e9b426dc7ca6e128b1
    Signed-off-by: Siyuan Wang <SiYuan.Wang at amd.com>
    Signed-off-by: Siyuan Wang <wangsiyuanbuaa at gmail.com>
 src/northbridge/amd/agesa/family15/northbridge.c | 9 ++++++++-
 src/northbridge/amd/agesa/family15/northbridge.h | 1 +
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c
index f297fc0..12a211f 100644
--- a/src/northbridge/amd/agesa/family15/northbridge.c
+++ b/src/northbridge/amd/agesa/family15/northbridge.c
@@ -846,7 +846,7 @@ static struct device_operations pci_domain_ops = {
 	.set_resources	  = domain_set_resources,
 	.enable_resources = domain_enable_resources,
 	.init		  = NULL,
-	.scan_bus	  = pci_domain_scan_bus,
+	.scan_bus	  = f15_pci_domain_scan_bus,
 	.ops_pci_bus	  = &pci_ops_mmconf,
@@ -1143,3 +1143,10 @@ struct chip_operations northbridge_amd_agesa_family15_root_complex_ops = {
 	CHIP_NAME("AMD FAM15 Root Complex")
 	.enable_dev = root_complex_enable_dev,
+/* all family15's pci devices are under 0x18.0, so we search from dev 0x18 fun 0 */
+static unsigned int f15_pci_domain_scan_bus(device_t dev, unsigned int max)
+	max = pci_scan_bus(dev->link_list, PCI_DEVFN(0x18, 0), 0xff, max);
+	return max;
diff --git a/src/northbridge/amd/agesa/family15/northbridge.h b/src/northbridge/amd/agesa/family15/northbridge.h
index 7606b32..cd9f83c 100644
--- a/src/northbridge/amd/agesa/family15/northbridge.h
+++ b/src/northbridge/amd/agesa/family15/northbridge.h
@@ -22,5 +22,6 @@
 static struct device_operations pci_domain_ops;
 static struct device_operations cpu_bus_ops;
+static unsigned int f15_pci_domain_scan_bus(device_t dev, unsigned int max);

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