[coreboot] Patch set updated for coreboot: 28ff105 Add support for Panther Point to SPI driver

Patrick Georgi (patrick@georgi-clan.de) gerrit at coreboot.org
Thu May 24 09:46:23 CEST 2012


Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1048

-gerrit

commit 28ff10529190051468e1d8e877e64f51e5054671
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Wed May 23 11:18:35 2012 -0700

    Add support for Panther Point to SPI driver
    
    Change-Id: I98b05d9e639eda880b6e8dc6398413d1f4f5e9c3
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/include/device/pci_ids.h        |    2 ++
 src/southbridge/intel/bd82x6x/spi.c |   29 ++++++++++++++++++++---------
 2 files changed, 22 insertions(+), 9 deletions(-)

diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 1765293..4ebd572 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -2504,6 +2504,8 @@
 
 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN	0x1c41
 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX	0x1c5f
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN 0x1e41
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX 0x1e5d
 #define PCI_DEVICE_ID_INTEL_TGP_LPC	0x27bc
 
 /* Intel 82801E (C-ICH) */
diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c
index 95fbfb9..ccc530d 100644
--- a/src/southbridge/intel/bd82x6x/spi.c
+++ b/src/southbridge/intel/bd82x6x/spi.c
@@ -286,11 +286,24 @@ void spi_free_slave(struct spi_slave *_slave)
 	free(slave);
 }
 
-static inline int spi_is_cougarpoint_lpc(uint16_t device_id)
+/*
+ * Check if this device ID matches one of supported Intel PCH devices.
+ *
+ * Return the ICH version if there is a match, or zero otherwise.
+ */
+static inline int get_ich_version(uint16_t device_id)
 {
-	return device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN &&
-		device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX;
-};
+	if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC)
+		return 7;
+
+	if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN &&
+	     device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) ||
+	    (device_id >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN &&
+	     device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX))
+		return 9;
+
+	return 0;
+}
 
 void spi_init(void)
 {
@@ -313,11 +326,9 @@ void spi_init(void)
 		return;
 	}
 
-	if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC) {
-		ich_version = 7;
-	} else if (spi_is_cougarpoint_lpc(device_id)) {
-		ich_version = 9;
-	} else {
+	ich_version = get_ich_version(device_id);
+
+	if (!ich_version) {
 		printk(BIOS_DEBUG, "ICH SPI: No known ICH found.\n");
 		return;
 	}




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