[coreboot] New patch to review for coreboot: e3e901d Modify DMI init for IvyBridge

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/969

-gerrit

commit e3e901db657591603411402a1ceb581873480442
Author: Vincent Palatin <vpalatin at chromium.org>
Date:   Wed Mar 28 16:10:29 2012 -0700

    Modify DMI init for IvyBridge
    
    The ASPM setting for the Direct Media Interface should no longer be done on
    Ivybridge/PantherPoint based systems.
    
    Change-Id: Id30de1beb1b162564048e76712736ccf7049dc7c
    Signed-off-by: Vincent Palatin <vpalatin at chromium.org>
---
 src/northbridge/intel/sandybridge/northbridge.c |   18 +++++++++++-------
 1 files changed, 11 insertions(+), 7 deletions(-)

diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index e3334c4..b1f7c72 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -347,10 +347,12 @@ static void northbridge_dmi_init(struct device *dev)
 	DMIBAR32(0x1d0) = 0xffffffff;
 
 	/* Steps prior to DMI ASPM */
-	reg32 = DMIBAR32(0x250);
-	reg32 &= ~((1 << 22)|(1 << 20));
-	reg32 |= (1 << 21);
-	DMIBAR32(0x250) = reg32;
+	if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
+		reg32 = DMIBAR32(0x250);
+		reg32 &= ~((1 << 22)|(1 << 20));
+		reg32 |= (1 << 21);
+		DMIBAR32(0x250) = reg32;
+	}
 
 	reg32 = DMIBAR32(0x238);
 	reg32 |= (1 << 29);
@@ -372,9 +374,11 @@ static void northbridge_dmi_init(struct device *dev)
 	}
 
 	/* Enable ASPM on SNB link, should happen before PCH link */
-	reg32 = DMIBAR32(0xd04);
-	reg32 |= (1 << 4);
-	DMIBAR32(0xd04) = reg32;
+	if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
+		reg32 = DMIBAR32(0xd04);
+		reg32 |= (1 << 4);
+		DMIBAR32(0xd04) = reg32;
+	}
 
 	reg32 = DMIBAR32(0x88);
 	reg32 |= (1 << 1) | (1 << 0);