[coreboot] Patch merged into coreboot/master: ed37431 Add support for RAM-less multi-processor init

gerrit at coreboot.org gerrit at coreboot.org
Sat Mar 31 11:57:52 CEST 2012

the following patch was just integrated into master:
commit ed3743123e4f832be6761a9b550cab5cc8a3f934
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Tue Feb 14 10:39:17 2012 +0200

    Add support for RAM-less multi-processor init
    For a hyper-threading processor, enabling cache requires that both the
    BSP and AP CPU clear CR0.CD (Cache Disable) bit. For a Cache-As-Ram
    implementation, partial multi-processor initialisation precedes
    raminit and AP CPUs' 16bit entry must be run from ROM.
    The AP CPU can only start execute real-mode code at a 4kB aligned
    address below 1MB. The protected mode entry code for AP is identical
    with the BSP code, which is already located at the top of bootblock.
    This patch takes the simplest approach and aligns the bootblock
    16 bit entry at highest possible 4kB boundary below 1MB.
    The symbol ap_sipi_vector is tested to match CONFIG_AP_SIPI_VECTOR
    used by the CAR code in romstage. Adress is not expected to ever
    change, but if it does, link will fail.
    Change-Id: I82e4edbf208c9ba863f51a64e50cd92871c528ef
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>

See http://review.coreboot.org/454 for details.


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