[coreboot] Patch merged into coreboot/master: ea52a94 MTRR: add alternate allocation method for odd memory maps

gerrit at coreboot.org gerrit at coreboot.org
Fri Mar 30 17:54:47 CEST 2012

the following patch was just integrated into master:
commit ea52a9429656c8b5004da212f4c2cc1fcfb52db9
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Dec 22 10:59:40 2011 -0800

    MTRR: add alternate allocation method for odd memory maps
    With >= 4GB memory installed we get a memory map split in the middle
    due to remap that has boundaries that are inconveniently aligned for
    MTRRs due to the various UMA regions.
    0000MB-2780MB  2780MB  RAM     (writeback)
    2780MB-2782MB     2MB  TSEG    (uncached/SMRR)
    2782MB-2784MB     2MB  GFX GTT (uncached)
    2784MB-2816MB    32MB  GFX UMA (uncached)
    2816MB-4096MB  1280MB  EMPTY   (N/A)
    4096MB-5368MB  1272MB  RAM     (writeback)
    5368MB-5376MB     8MB  ME UMA  (uncached)
    The default MTRR allocation method of trying to cover everything
    with one MTRR and then carve out a single uncached region does
    not work for the GPU aperture which needs write-combining type,
    and it also has issues trying to cover the uneven boundaries
    in the avaiable variable MTRRs.
    My goal was to make a minimal set of changes and avoid modifying
    behavior on existing systems with an algorithm that is not always
    optimal for a typical memory layout.  So the flag 'above4gb=2'
    will change these allocation behaviors:
    1) Detect the number of available variable MTRRs rather than
    limiting to hardcoded value.  We need every last MTRR.
    2) Don't try to cover all RAM with one MTRR, instead let each
    RAM region get covered independently.
    3) Don't assume uma_memory_base is part of the last region
    and increase the size of that region.  In this case the UMA
    region is carved out from the lower memory region and it is
    already declared as part of the ram region.
    4) If a memory region can't be covered with MTRRs >= 16MB then
    instead make a larger region and trim it with uncached MTRRs.
    Change-Id: I5a60a44ab6d3ae2f46ea6ffa9e3677aaad2485eb
    Signed-off-by: Duncan Laurie <dlaurie at google.com>

Build-Tested: build bot (Jenkins) at Fri Mar 30 11:22:00 2012, giving +1
See http://review.coreboot.org/761 for details.


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