[coreboot] Fwd: porting Coreboot to a new motherboard....

Kyösti Mälkki kyosti.malkki at gmail.com
Wed Mar 28 15:55:04 CEST 2012

On Wed, 2012-03-28 at 17:22 +0430, ali hagigat wrote:
> I just added 10 "nop" assembly command("no operation")!
> 10 because the number of the Pentium III pipeline stages is 10.
> Very simple and strange. After adding that, each time hardwaremain()
> got executed and the code continued loading FILO.

Try to use original coreboot tree, with your raminit of course, but this
time do not enable RAM cache for 0x0-CONFIG_RAMTOP range. That is
typically the (variable) MTRR 0 setting close to the end of


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