[coreboot] asus l1n64 - this is damn Nvidia
Marc Jones
marcj303 at gmail.com
Mon Mar 26 23:48:01 CEST 2012
Hi Julian,
On Sun, Mar 25, 2012 at 3:09 PM, Julian Shulika <hercares at gmail.com> wrote:
>
>
> ---------- Forwarded message ----------
> From: Julian Shulika <hercares at gmail.com>
> Date: 2012/3/26
> Subject: Re: coreboot and opteron 8431
> To: Arne Georg Gleditsch <arne at gledits.ch>
>
>
> I tried to port asus l1n64 more than one year. This board also based on
> mcp55,this is only one board for AMD 4x4 platform. It differs from other
> similar board by different scheme
>
>
> Tyan S2912, supermicro h8dmr have
> connection diagram, if I use just cpu0,I can't use second mcp55 mcp55
> <->cpu1 <-> cpu0 <-> mcp55
>
>
> Asus L1N64 has different connection diagram mcp55 <->
> mcp55<->cpu0 <-> cpu1
> I saw your posts when you try to help guy with supermicro board,but
> I'm stuck in one place,because I have not reached to memory init, I think
> it's because of wrong devicetree. Could you please look at lspci output, may
> be you can see something...
> Thanks for your work done
The devicetree isn't really used prior to memory init. Most of what
you should examine is called in romstage.c.
Marc
>
> chip northbridge/amd/amdfam10/root_complex # Root complex
> device lapic_cluster 0 on # (L)APIC cluster
> chip cpu/amd/socket_F_1207 # CPU socket
> device lapic 0 on end # Local APIC of the CPU
> end
> end
> device pci_domain 0 on # PCI domain
> subsystemid 0x10de 0x81fb inherit
> chip northbridge/amd/amdfam10 # Northbridge / RAM controller
> device pci 18.0 on end
> device pci 18.0 on end
> chip southbridge/nvidia/mcp55 # Southbridge
> device pci 0.0 on end # HT
> device pci 1.0 on end # LPC
> device pci 1.1 on end # LPC
> device pci 5.1 on end # SATA 1
> device pci 5.2 on end # SATA 2
> device pci a.0 off end # PCI E 5
> device pci f.0 off end # PCI E 5
> end
> device pci 18.0 on # SB on link 2
> chip southbridge/nvidia/mcp55 # Southbridge
> device pci 0.0 on end # HT
> device pci 1.0 on # LPC
> chip superio/ite/it8716f # Super I/O
> device pnp 2e.0 on # Floppy
> io 0x60 = 0x3f0
> irq 0x70 = 6
> drq 0x74 = 2
> end
> device pnp 2e.1 on # Com1
> io 0x60 = 0x3f8
> irq 0x70 = 4
> end
> device pnp 2e.2 off # Com2 (N/A)
> end
> device pnp 2e.3 on # Parallel port
> io 0x60 = 0x378
> io 0x62 = 0x000
> irq 0x70 = 7
> drq 0x74 = 4
> end
> device pnp 2e.4 on # Environment controller
> io 0x60 = 0x290
> io 0x62 = 0x000
> irq 0x70 = 0
> end
> device pnp 2e.5 on # PS/2 keyboard
> io 0x60 = 0x60
> io 0x62 = 0x64
> irq 0x70 = 1 # PS/2 keyboard IRQ
> end
> device pnp 2e.6 on # PS/2 mouse
> irq 0x70 = 12 # PS/2 mouse IRQ
> end
> device pnp 2e.7 off # GPIO
> io 0x60 = 0x0000 # SMI# Normal Run Access
> io 0x62 = 0x800 # Simple I/O
> io 0x64 = 0x0000 # Serial Flash I/F
> end
> device pnp 2e.8 off # MIDI (N/A)
> end
> device pnp 2e.9 off # Game port (N/A)
> end
> device pnp 2e.a off # Consumer IR (N/A)
> end
> end # Super I/O
> end
> device pci 1.1 on # SM 0
> chip drivers/generic/generic # DIMM 0-0-0
> device i2c 50 on end
> end
> chip drivers/generic/generic # DIMM 0-0-1
> device i2c 51 on end
> end
> chip drivers/generic/generic # DIMM 0-1-0
> device i2c 52 on end
> end
> chip drivers/generic/generic # DIMM 0-1-1
> device i2c 53 on end
> end
>
> end
>
> device pci 2.0 on end # USB 1.1
> device pci 2.1 on end # USB 2
> device pci 4.0 on end # IDE
> device pci 5.0 on end # SATA 0
> device pci 5.1 on end # SATA 1
> device pci 5.2 on end # SATA 2
> device pci 6.0 on # PCI
> device pci 6.0 on end
> end
> device pci 6.1 on end # AZA
> device pci 8.0 on end # NIC
> device pci 9.0 on end # NIC
> device pci a.0 on end # PCI E 5
> device pci d.0 on end # PCI E 2
> device pci e.0 on end # PCI E 1
> device pci f.0 on end # PCI E 0
> register "ide0_enable" = "1"
> register "sata0_enable" = "1"
> register "sata1_enable" = "1"
> # 1: SMBus under 2e.8, 2: SM0 3: SM1
> register "mac_eeprom_smbus" = "3"
> register "mac_eeprom_addr" = "0x51"
> end
> end
> device pci 18.1 on end
> device pci 18.2 on end
> device pci 18.3 on end
> device pci 18.4 on end
> end
> end
> # chip drivers/generic/debug
> # device pnp 0.0 off end # chip name
> # device pnp 0.1 on end # pci_regs_all
> # device pnp 0.2 on end # mem
> # device pnp 0.3 off end # cpuid
> # device pnp 0.4 on end # smbus_regs_all
> # device pnp 0.5 off end # dual core msr
> # device pnp 0.6 off end # cache size
> # device pnp 0.7 off end # tsc
> # device pnp 0.8 off end # io
> # device pnp 0.9 off end # io
> # end
> end
>
>
>
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