[coreboot] GSoC project ideas

[Peter Stuge]

Carl-Daniel Hailfinger wrote:
> Tools which would help developers, usable .. with current hardware.

I think the best way is to put them on the Talk:GSoC wiki page. Ie.
not on the GSoC page itself, but on the discussion page for that
page.


> - Flash ICE device with SPI support.
> - Flash ICE device with LPC/FWH support.
> - Serial emulation for LPC buses on a configurable I/O port with
> USB output on the other side.

Sure. If there are students with a hardware interest I think these
are good projects. There is also much VHDL available already.


> As a basis for all those ideas I'd propose the Openbench logic sniffer.

Yes and no. OLS is fine as a prototyping and development platform for
these projects, but it's an incredibly poor design when it comes to
USB, and it doesn't fit in the expansion slot.


> It has a fast FPGA, enough gates and roughly 32 kByte RAM.

The RAM is block RAM inside the FPGA, which can not be arbitrarily
used from logic. The OLS doesn't have a separate RAM chip. One needs
to be connected externally. It's not impossible, but requires some
soldering skill.


> we could easily attach a fast (66+ MHz) SPI flash chip to it.

The OLS as SPI master mux for having an easy way to flash a real chip
used by a mainboard when booting is fine. But the chip should be able
to reside on the mainboard, and the OLS should drive the mainboard
reset while flashing. Having the OLS connect via wires means that the
SPI flash can not be driven quite so fast. The shorter wires the
better. The OLS is a big board with exposed contacts on the bottom.

The OLS is not a good fit for installation into e.g. a laptop. This
is one of the use cases for a QiProg; it's intended to be soldered
into the target system, on top of, or very near, the flash chip.


> All of those projects would not result in any coreboot code, but
> they would make development easier,

I think this is fine, and we've had similar project ideas already.
Also some of our previous running projects have resulted in code
outside of coreboot but which complements coreboot significantly.
Assisting development counts too.


> now that we're porting coreboot to laptops where a LPC bus may be
> the only easily available bus at startup.

I don't know that LPC is usually available, but even so it is a nice
start, and VHDL already exists.


> Do we have mentors who can review VHDL/Verilog?

Yes.


//Peter