[coreboot] Patch set updated for coreboot: 145f98d Make PCI CONF2 support a compile time option.

Stefan Reinauer (stefan.reinauer@coreboot.org) gerrit at coreboot.org
Fri Mar 9 02:22:44 CET 2012


Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/758

-gerrit

commit 145f98d5d05619cebdb882382a1b8c4dc61304e4
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Thu Nov 17 13:05:31 2011 -0800

    Make PCI CONF2 support a compile time option.
    
    It's not used on any board supported by coreboot but has been
    detected at run time since ages. No new boards (since 2000?)
    are using the CONF2 method, so it is unlikely we ever have to
    turn this on for a board.
    
    Change-Id: I17df94a8a77b9338fde10a6b114b44d393776e66
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/arch/x86/Kconfig            |    4 ++++
 src/arch/x86/lib/Makefile.inc   |    4 +---
 src/arch/x86/lib/pci_ops_auto.c |    9 ++++++++-
 3 files changed, 13 insertions(+), 4 deletions(-)

diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index 078ae95..bc01c9c 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -96,4 +96,8 @@ config LITTLE_ENDIAN
 	bool
 	default !BIG_ENDIAN
 
+config PCI_CONF2
+	bool
+	default n
+
 endmenu
diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc
index 3f4dc95..96fb9b0 100644
--- a/src/arch/x86/lib/Makefile.inc
+++ b/src/arch/x86/lib/Makefile.inc
@@ -1,10 +1,8 @@
 ramstage-y += c_start.S
 ramstage-y += cpu.c
 ramstage-y += pci_ops_conf1.c
-ramstage-y += pci_ops_conf2.c
-
+ramstage-$(CONFIG_PCI_CONF2) += pci_ops_conf2.c
 ramstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c
-
 ramstage-y += pci_ops_auto.c
 ramstage-y += exception.c
 ramstage-$(CONFIG_IOAPIC) += ioapic.c
diff --git a/src/arch/x86/lib/pci_ops_auto.c b/src/arch/x86/lib/pci_ops_auto.c
index 92eedd3..58e098b 100644
--- a/src/arch/x86/lib/pci_ops_auto.c
+++ b/src/arch/x86/lib/pci_ops_auto.c
@@ -6,6 +6,7 @@
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 
+#if CONFIG_PCI_CONF2
 /*
  * Before we decide to use direct hardware access mechanisms, we try to do some
  * trivial checks to ensure it at least _seems_ to be working -- we just test
@@ -41,7 +42,7 @@ static int pci_sanity_check(const struct pci_bus_operations *o)
 	return 0;
 }
 
-struct pci_bus_operations *pci_bus_fallback_ops = NULL;
+static struct pci_bus_operations *pci_bus_fallback_ops = NULL;
 
 static const struct pci_bus_operations *pci_check_direct(void)
 {
@@ -89,6 +90,12 @@ const struct pci_bus_operations *pci_remember_direct(void)
 		pci_bus_fallback_ops = (struct pci_bus_operations *)pci_check_direct();
 	return pci_bus_fallback_ops;
 }
+#else
+const struct pci_bus_operations *pci_remember_direct(void)
+{
+	return &pci_cf8_conf1;
+}
+#endif
 
 /** Set the method to be used for PCI, type I or type II
  */




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