[coreboot] Patch set updated for coreboot: 95dc6ef Unify IO APIC address specification
Patrick Georgi (patrick@georgi-clan.de)
gerrit at coreboot.org
Wed Mar 7 13:06:42 CET 2012
Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/677
-gerrit
commit 95dc6efcd0601d90a4a3ea89ce44f4293b78a11b
Author: Patrick Georgi <patrick at georgi-clan.de>
Date: Thu Feb 16 18:54:37 2012 +0100
Unify IO APIC address specification
Some places still hardcoded the address instead of using IO_APIC_ADDR.
Change-Id: I3941c1ff62972ce56a5bc466eab7134f901773d3
Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
src/mainboard/amd/torpedo/platform_cfg.h | 2 +-
src/mainboard/iwave/iWRainbowG6/mptable.c | 2 +-
src/northbridge/intel/i945/acpi/hostbridge.asl | 3 ++-
src/northbridge/intel/sch/acpi/hostbridge.asl | 3 ++-
src/southbridge/amd/cimx/sb700/lpc.c | 5 +++--
src/southbridge/amd/cimx/sb800/lpc.c | 5 +++--
src/southbridge/amd/cimx/sb900/lpc.c | 5 +++--
src/southbridge/amd/sb800/lpc.c | 4 ++--
src/southbridge/amd/sb800/sm.c | 8 +++-----
src/southbridge/intel/sch/lpc.c | 5 +++--
10 files changed, 23 insertions(+), 19 deletions(-)
diff --git a/src/mainboard/amd/torpedo/platform_cfg.h b/src/mainboard/amd/torpedo/platform_cfg.h
index d97d034..cf31c6a 100644
--- a/src/mainboard/amd/torpedo/platform_cfg.h
+++ b/src/mainboard/amd/torpedo/platform_cfg.h
@@ -137,7 +137,7 @@
* @section WatchDogTimerBase
*/
// #ifndef WATCHDOG_TIMER_BASE_ADDRESS
-// #define WATCHDOG_TIMER_BASE_ADDRESS 0xFEC00000
+// #define WATCHDOG_TIMER_BASE_ADDRESS IO_APIC_ADDR
// #endif
/**
diff --git a/src/mainboard/iwave/iWRainbowG6/mptable.c b/src/mainboard/iwave/iWRainbowG6/mptable.c
index 953f16a..87de022 100644
--- a/src/mainboard/iwave/iWRainbowG6/mptable.c
+++ b/src/mainboard/iwave/iWRainbowG6/mptable.c
@@ -34,7 +34,7 @@ void *smp_write_config_table(void *v)
smp_write_processors(mc);
mptable_write_buses(mc, NULL, &isa_bus);
- smp_write_ioapic(mc, 2, 0x20, 0xfec00000);
+ smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
{
device_t dev;
struct resource *res;
diff --git a/src/northbridge/intel/i945/acpi/hostbridge.asl b/src/northbridge/intel/i945/acpi/hostbridge.asl
index a76d8e2..8dcadd7 100644
--- a/src/northbridge/intel/i945/acpi/hostbridge.asl
+++ b/src/northbridge/intel/i945/acpi/hostbridge.asl
@@ -19,6 +19,7 @@
* MA 02110-1301 USA
*/
+#include <arch/ioapic.h>
Name(_HID,EISAID("PNP0A08")) // PCIe
Name(_CID,EISAID("PNP0A03")) // PCI
@@ -211,7 +212,7 @@ Method (_CRS, 0, Serialized)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x00000000, 0xfebfffff, 0x00000000,
- 0xfec00000,,, PM01)
+ IO_APIC_ADDR,,, PM01)
// TPM Area (0xfed40000-0xfed44fff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
diff --git a/src/northbridge/intel/sch/acpi/hostbridge.asl b/src/northbridge/intel/sch/acpi/hostbridge.asl
index 7e92a0e..44a8be0 100644
--- a/src/northbridge/intel/sch/acpi/hostbridge.asl
+++ b/src/northbridge/intel/sch/acpi/hostbridge.asl
@@ -19,6 +19,7 @@
* MA 02110-1301 USA
*/
+#include <arch/ioapic.h>
Name(_HID,EISAID("PNP0A08")) // PCIe
Name(_CID,EISAID("PNP0A03")) // PCI
@@ -211,7 +212,7 @@ Method (_CRS, 0, Serialized)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x00000000, 0xfebfffff, 0x00000000,
- 0xfec00000,,, PM01)
+ IO_APIC_ADDR,,, PM01)
// TPM Area (0xfed40000-0xfed44fff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
diff --git a/src/southbridge/amd/cimx/sb700/lpc.c b/src/southbridge/amd/cimx/sb700/lpc.c
index e43193a..7157a55 100644
--- a/src/southbridge/amd/cimx/sb700/lpc.c
+++ b/src/southbridge/amd/cimx/sb700/lpc.c
@@ -21,6 +21,7 @@
#include "lpc.h"
#include <bitops.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <console/console.h> /* printk */
#include <cbmem.h>
@@ -61,8 +62,8 @@ void lpc_read_resources(device_t dev)
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
- res = new_resource(dev, 3); /* IOAPIC */
- res->base = 0xfec00000;
+ res = new_resource(dev, 3);
+ res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
diff --git a/src/southbridge/amd/cimx/sb800/lpc.c b/src/southbridge/amd/cimx/sb800/lpc.c
index bc643b5..856b8b3 100644
--- a/src/southbridge/amd/cimx/sb800/lpc.c
+++ b/src/southbridge/amd/cimx/sb800/lpc.c
@@ -19,6 +19,7 @@
#include <console/console.h>
#include <device/pci.h>
+#include <arch/ioapic.h>
#include "lpc.h"
@@ -45,8 +46,8 @@ void lpc_read_resources(device_t dev)
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
- res = new_resource(dev, 3); /* IOAPIC */
- res->base = 0xfec00000;
+ res = new_resource(dev, 3);
+ res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
diff --git a/src/southbridge/amd/cimx/sb900/lpc.c b/src/southbridge/amd/cimx/sb900/lpc.c
index 48bfe36..9873d37 100644
--- a/src/southbridge/amd/cimx/sb900/lpc.c
+++ b/src/southbridge/amd/cimx/sb900/lpc.c
@@ -20,6 +20,7 @@
#include <device/pci.h>
#include "lpc.h"
#include <console/console.h> /* printk */
+#include <arch/ioapic.h>
void lpc_read_resources(device_t dev)
@@ -45,8 +46,8 @@ void lpc_read_resources(device_t dev)
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
- res = new_resource(dev, 3); /* IOAPIC */
- res->base = 0xfec00000;
+ res = new_resource(dev, 3);
+ res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
diff --git a/src/southbridge/amd/sb800/lpc.c b/src/southbridge/amd/sb800/lpc.c
index 6b72a62..4e2031f 100644
--- a/src/southbridge/amd/sb800/lpc.c
+++ b/src/southbridge/amd/sb800/lpc.c
@@ -91,8 +91,8 @@ static void sb800_lpc_read_resources(device_t dev)
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
- //res = new_resource(dev, 3); /* IOAPIC */
- //res->base = 0xfec00000;
+ //res = new_resource(dev, 3);
+ //res->base = IO_APIC_ADDR;
//res->size = 0x00001000;
//res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
diff --git a/src/southbridge/amd/sb800/sm.c b/src/southbridge/amd/sb800/sm.c
index 9347c42..50a8f0b 100644
--- a/src/southbridge/amd/sb800/sm.c
+++ b/src/southbridge/amd/sb800/sm.c
@@ -84,16 +84,14 @@
static void sm_init(device_t dev)
{
u8 byte;
- u32 ioapic_base;
printk(BIOS_INFO, "sm_init().\n");
- ioapic_base = 0xFEC00000;//pci_read_config32(dev, 0x74) & (0xffffffe0); /* some like mem resource, but does not have enable bit */
/* Don't rename APIC ID */
/* TODO: We should call setup_ioapic() here. But kernel hangs if cpu is K8.
* We need to check out why and change back. */
- clear_ioapic(ioapic_base);
- //setup_ioapic(ioapic_base, 0);
+ clear_ioapic(IO_APIC_ADDR);
+ //setup_ioapic(IO_APIC_ADDR, 0);
/* enable serial irq */
byte = pm_ioread(0x54);
@@ -277,7 +275,7 @@ static void sb800_sm_read_resources(device_t dev)
/* apic */
res = new_resource(dev, 0x74);
- res->base = 0xfec00000;
+ res->base = IO_APIC_ADDR;
res->size = 256 * 0x10;
res->limit = 0xFEFFFFFUL; /* res->base + res->size -1; */
res->align = 8;
diff --git a/src/southbridge/intel/sch/lpc.c b/src/southbridge/intel/sch/lpc.c
index ab180bb..977e01b 100644
--- a/src/southbridge/intel/sch/lpc.c
+++ b/src/southbridge/intel/sch/lpc.c
@@ -23,6 +23,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include "chip.h"
/* SCH LPC defines */
@@ -164,8 +165,8 @@ static void sch_lpc_read_resources(device_t dev)
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
- res = new_resource(dev, 3); /* IOAPIC */
- res->base = 0xfec00000;
+ res = new_resource(dev, 3);
+ res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
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