[coreboot] New patch to review for coreboot: e3d53a2 Add support for the Startech PEX1XS1PMINI

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/690

-gerrit

commit e3d53a2242c3c6dd522c58ad05a74847be80fa84
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Mon May 9 15:19:29 2011 -0700

    Add support for the Startech PEX1XS1PMINI
    
    It has a smaller footprint than the already supported MPEX2S952
    
    Change-Id: Ie36b67f9628882d516ca34ff164f0e8918955a5b
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
    Tested-by: Stefan Reinauer <reinauer at google.com>
    Reviewed-by: Duncan Laurie <dlaurie at google.com>
---
 src/drivers/oxford/oxpcie/oxpcie.c       |    6 ++++++
 src/drivers/oxford/oxpcie/oxpcie_early.c |   26 +++++++++++++++++++++++---
 src/lib/uart8250mem.c                    |    2 ++
 3 files changed, 31 insertions(+), 3 deletions(-)

diff --git a/src/drivers/oxford/oxpcie/oxpcie.c b/src/drivers/oxford/oxpcie/oxpcie.c
index 94c5b64..e1fb65f 100644
--- a/src/drivers/oxford/oxpcie/oxpcie.c
+++ b/src/drivers/oxford/oxpcie/oxpcie.c
@@ -54,3 +54,9 @@ static const struct pci_driver oxford_oxpcie_driver __pci_driver = {
 	.vendor = 0x1415,
 	.device = 0xc158,
 };
+
+static const struct pci_driver oxford_oxpcie_driver_2 __pci_driver = {
+	.ops    = &oxford_oxpcie_ops,
+	.vendor = 0x1415,
+	.device = 0xc11b,
+};
diff --git a/src/drivers/oxford/oxpcie/oxpcie_early.c b/src/drivers/oxford/oxpcie/oxpcie_early.c
index 3480654..2c7767e 100644
--- a/src/drivers/oxford/oxpcie/oxpcie_early.c
+++ b/src/drivers/oxford/oxpcie/oxpcie_early.c
@@ -31,6 +31,9 @@
 #define OXPCIE_DEVICE \
 	PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 0)
 
+#define OXPCIE_DEVICE_3 \
+	PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 3)
+
 void oxford_init(void)
 {
 	u16 reg16;
@@ -72,14 +75,31 @@ void oxford_init(void)
 	while ((id == 0) || (id == 0xffffffff))
 		id = pci_read_config32(OXPCIE_DEVICE, PCI_VENDOR_ID);
 
+	u32 device = OXPCIE_DEVICE; /* unknown default */
+	switch (id) {
+	case 0xc1181415: /* e.g. Startech PEX1S1PMINI */
+		/* On this device function 0 is the parallel port, and
+		 * function 3 is the serial port. So let's go look for
+		 * the UART.
+		 */
+		id = pci_read_config32(OXPCIE_DEVICE_3, PCI_VENDOR_ID);
+		if (id != 0xc11b1415)
+			return;
+		device = OXPCIE_DEVICE_3;
+		break;
+	case 0xc1581415: /* e.g. Startech MPEX2S952 */
+		device = OXPCIE_DEVICE;
+		break;
+	}
+
 	/* Setup base address on device */
-	pci_write_config32(OXPCIE_DEVICE, PCI_BASE_ADDRESS_0,
+	pci_write_config32(device, PCI_BASE_ADDRESS_0,
 				CONFIG_OXFORD_OXPCIE_BASE_ADDRESS);
 
 	/* Enable memory on device */
-	reg16 = pci_read_config16(OXPCIE_DEVICE, PCI_COMMAND);
+	reg16 = pci_read_config16(device, PCI_COMMAND);
 	reg16 |= PCI_COMMAND_MEMORY;
-	pci_write_config16(OXPCIE_DEVICE, PCI_COMMAND, reg16);
+	pci_write_config16(device, PCI_COMMAND, reg16);
 
 	/* Now the UART initialization */
 	u32 uart0_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000;
diff --git a/src/lib/uart8250mem.c b/src/lib/uart8250mem.c
index 75d51ff..a38623e 100644
--- a/src/lib/uart8250mem.c
+++ b/src/lib/uart8250mem.c
@@ -117,6 +117,8 @@ u32 uart_mem_init(void)
 
 #if defined(MORE_TESTING) && !defined(__SMM__) && !defined(__PRE_RAM__)
 	device_t dev = dev_find_device(0x1415, 0xc158, NULL);
+	if (!dev)
+		dev = dev_find_device(0x1415, 0xc11b, NULL);
 
 	if (dev) {
 		struct resource *res = find_resource(dev, 0x10);