[coreboot] New patch to review for coreboot: 691d404 Intel cpus: Extend cache to cover complete Flash Device

[Kyösti Mälkki (kyosti.malkki@gmail.com)]

Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1146

-gerrit

commit 691d404408da286b4ea0d2ea80c4d54de63b9b8f
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Thu Jun 28 21:37:45 2012 +0300

    Intel cpus: Extend cache to cover complete Flash Device
    
    CACHE_ROM_SIZE default is ROM_SIZE, the Flash device size set
    in menuconfig. This fixes a case where 8 MB SPI flash MTRR setup
    would not cover the bottom 4 MB when ramstage is decompressed.
    
    Verify CACHE_ROM_SIZE has 4kB granularity.
    One may set CACHE_ROM_SIZE==0 to disable this cache.
    
    Change-Id: Ib2b4ea528a092b96ff954894e60406d64f250783
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/cpu/intel/car/cache_as_ram_ht.inc      |    9 +++++----
 src/cpu/intel/model_206ax/cache_as_ram.inc |    8 ++++++--
 src/cpu/intel/model_6ex/cache_as_ram.inc   |   10 +++++++---
 3 files changed, 18 insertions(+), 9 deletions(-)

diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc
index 4e0f391..dc1cfc9 100644
--- a/src/cpu/intel/car/cache_as_ram_ht.inc
+++ b/src/cpu/intel/car/cache_as_ram_ht.inc
@@ -30,9 +30,6 @@
 #define LAPIC(x)		$(LAPIC_DEFAULT_BASE | LAPIC_ ## x)
 #define START_IPI_VECTOR	((CONFIG_AP_SIPI_VECTOR >> 12) & 0xff)
 
-/* Base address to cache all of Flash ROM, just below 4GB. */
-#define CACHE_ROM_BASE	((1<<22 - CONFIG_CACHE_ROM_SIZE>>10)<<10)
-
 #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
 #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
 
@@ -380,6 +377,9 @@ no_msr_11e:
 	movl	$(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax
 	wrmsr
 
+#if CONFIG_CACHE_ROM_SIZE
+#define CACHE_ROM_SIZE	(CONFIG_CACHE_ROM_SIZE & ~0x3ff)
+#define CACHE_ROM_BASE	((1<<22 - CONFIG_CACHE_ROM_SIZE>>10)<<10)
 	/* Enable caching and Speculative Reads for Flash ROM device. */
 	movl	$MTRRphysBase_MSR(1), %ecx
 	movl	$(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax
@@ -387,8 +387,9 @@ no_msr_11e:
 	wrmsr
 	movl	$MTRRphysMask_MSR(1), %ecx
 	rdmsr
-	movl	$(~(CONFIG_CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
+	movl	$(~(CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
 	wrmsr
+#endif
 
 	post_code(0x39)
 
diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc
index 33246ff..0a41482 100644
--- a/src/cpu/intel/model_206ax/cache_as_ram.inc
+++ b/src/cpu/intel/model_206ax/cache_as_ram.inc
@@ -259,17 +259,21 @@ before_romstage:
 	movl	$CPU_PHYSMASK_HI, %edx	// 36bit address space
 	wrmsr
 
+#if CONFIG_CACHE_ROM_SIZE
+#define CACHE_ROM_SIZE	(CONFIG_CACHE_ROM_SIZE & ~0x3ff)
+#define CACHE_ROM_BASE	((1<<22 - CONFIG_CACHE_ROM_SIZE>>10)<<10)
 	/* Enable Caching and speculative Reads for the
 	 * complete ROM now that we actually have RAM.
 	 */
 	movl	$MTRRphysBase_MSR(1), %ecx
-	movl	$(0xffc00000 | MTRR_TYPE_WRPROT), %eax
+	movl	$(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax
 	xorl	%edx, %edx
 	wrmsr
 	movl	$MTRRphysMask_MSR(1), %ecx
-	movl	$(~(4*1024*1024 - 1) | MTRRphysMaskValid), %eax
+	movl	$(~(CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
 	movl	$CPU_PHYSMASK_HI, %edx
 	wrmsr
+#endif
 
 	post_code(0x39)
 
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index bdefb21..b134bfb 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -191,15 +191,19 @@ clear_mtrrs:
 	movl	$CPU_PHYSMASK_HI, %edx
 	wrmsr
 
-	/* Enable caching and Speculative Reads for the last 4MB. */
+#if CONFIG_CACHE_ROM_SIZE
+#define CACHE_ROM_SIZE	(CONFIG_CACHE_ROM_SIZE & ~0x3ff)
+#define CACHE_ROM_BASE	((1<<22 - CONFIG_CACHE_ROM_SIZE>>10)<<10)
+	/* Enable caching and Speculative Reads for Flash ROM device. */
 	movl	$MTRRphysBase_MSR(1), %ecx
-	movl	$(0xffc00000 | MTRR_TYPE_WRPROT), %eax
+	movl	$(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax
 	xorl	%edx, %edx
 	wrmsr
 	movl	$MTRRphysMask_MSR(1), %ecx
-	movl	$(~(4 * 1024 * 1024 - 1) | MTRRphysMaskValid), %eax
+	movl	$(~(CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
 	movl	$CPU_PHYSMASK_HI, %edx
 	wrmsr
+#endif
 
 	post_code(0x39)