[coreboot] New patch to review for coreboot: 44d75d5 Enable Intel PECI on Model 6fx CPUs

[Sven Schnelle (svens@stackframe.org)]

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1104

-gerrit

commit 44d75d5ad414de65861f7f9e59fb0bd7891ca138
Author: Sven Schnelle <svens at stackframe.org>
Date:   Tue Jun 19 18:00:01 2012 +0200

    Enable Intel PECI on Model 6fx CPUs
    
    Those CPUs support the PECI (Platform Environment Control
    Interface), so enable it. This interface is commonly used
    for tasks like fan control.
    
    Change-Id: Id2dadc4821de8cc0b579e77235aa36892e57fd02
    Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/cpu/intel/model_6fx/model_6fx_init.c |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
index 033dfe6..106719e 100644
--- a/src/cpu/intel/model_6fx/model_6fx_init.c
+++ b/src/cpu/intel/model_6fx/model_6fx_init.c
@@ -127,6 +127,8 @@ static void configure_c_states(void)
 }
 
 #define IA32_MISC_ENABLE	0x1a0
+#define IA32_PECI_CTL		0x5a0
+
 static void configure_misc(void)
 {
 	msr_t msr;
@@ -170,6 +172,12 @@ static void configure_misc(void)
 	msr.lo |= vid_max;
 
 	wrmsr(IA32_PERF_CTL, msr);
+
+	/* Enable PECI */
+	msr = rdmsr(IA32_PECI_CTL);
+	msr.lo |= 1;
+	wrmsr(IA32_PECI_CTL, msr);
+
 }
 
 #define PIC_SENS_CFG	0x1aa