[coreboot] New patch to review for coreboot: 2551459 Random VIA fixups to make it faster or non-crashing

[Rudolf Marek (r.marek@assembler.cz)]

Rudolf Marek (r.marek at assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1097

-gerrit

commit 255145949fe31a194c8e47b0af0d73b6775907c3
Author: Rudolf Marek <r.marek at assembler.cz>
Date:   Tue Jun 5 00:31:09 2012 +0200

    Random VIA fixups to make it faster or non-crashing
    
    IOAPIC uses now read32/write32 which is redirected, possibly even better is to use common IOAPIC setup
    ditch out the dump of PCI space, it takes way a lot time with serialICE.
    
    Change-Id: I029091973cee3dafc39a8d4b18aae4d8c6d10127
    Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
---
 src/southbridge/via/k8t890/pcie.c      |    7 ++++++-
 src/southbridge/via/k8t890/traf_ctrl.c |   14 +++++++-------
 src/southbridge/via/vt8237r/vt8237r.c  |    2 ++
 3 files changed, 15 insertions(+), 8 deletions(-)

diff --git a/src/southbridge/via/k8t890/pcie.c b/src/southbridge/via/k8t890/pcie.c
index 2840bf3..6ec1c41 100644
--- a/src/southbridge/via/k8t890/pcie.c
+++ b/src/southbridge/via/k8t890/pcie.c
@@ -35,6 +35,11 @@ static void pcie_common_init(struct device *dev)
 {
 	u8 reg;
 	int i, up;
+#if CONFIG_ULINUX
+	int loops = 2;
+#else
+	int loops = 1000;
+#endif
 
 	/* Disable downstream read cycle retry,
 	 * otherwise the bus scan will hang if no device is plugged in. */
@@ -64,7 +69,7 @@ static void pcie_common_init(struct device *dev)
 
 	/* Wait up to 100ms for link to come up */
 	up = 0;
-	for (i=0; i<1000; i++) {
+	for (i=0; i<loops; i++) {
 		if (pci_read_config16(dev, 0x52) & (1<<13)) {
 			up = 1;
 			break;
diff --git a/src/southbridge/via/k8t890/traf_ctrl.c b/src/southbridge/via/k8t890/traf_ctrl.c
index d3ed1e7..c55052c 100644
--- a/src/southbridge/via/k8t890/traf_ctrl.c
+++ b/src/southbridge/via/k8t890/traf_ctrl.c
@@ -21,6 +21,7 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <console/console.h>
+#include <arch/io.h>
 #include "k8t890.h"
 
 extern unsigned long log2(unsigned long x);
@@ -96,14 +97,13 @@ static void traf_ctrl_enable_generic(struct device *dev)
 	apic = (u32 *)K8T890_APIC_BASE;
 
 	/* Set APIC to FSB transported messages. */
-	apic[0] = 3;
-	data = apic[4];
-	apic[4] = (data & 0xFFFFFE) | 1;
-
+	write32(K8T890_APIC_BASE, 3);
+	data = read32(K8T890_APIC_BASE + 0x10);
+	write32(K8T890_APIC_BASE + 0x10, (data & 0xFFFFFE) | 1);
 	/* Set APIC ID. */
-	apic[0] = 0;
-	data = apic[4];
-	apic[4] = (data & 0xF0FFFF) | (K8T890_APIC_ID << 24);
+	write32(K8T890_APIC_BASE, 0);
+	data = read32(K8T890_APIC_BASE + 0x10);
+	write32(K8T890_APIC_BASE + 0x10, (data & 0xF0FFFF) | (K8T890_APIC_ID << 24));
 }
 
 static void traf_ctrl_enable_k8m890(struct device *dev)
diff --git a/src/southbridge/via/vt8237r/vt8237r.c b/src/southbridge/via/vt8237r/vt8237r.c
index 586df66..c8eaca1 100644
--- a/src/southbridge/via/vt8237r/vt8237r.c
+++ b/src/southbridge/via/vt8237r/vt8237r.c
@@ -54,6 +54,7 @@ void writeback(struct device *dev, u16 where, u8 what)
 
 void dump_south(device_t dev)
 {
+#if CONFIG_ULINUX == 0
 	int i, j;
 
 	for (i = 0; i < 256; i += 16) {
@@ -62,6 +63,7 @@ void dump_south(device_t dev)
 			printk(BIOS_DEBUG, "%02x ", pci_read_config8(dev, i + j));
 		printk(BIOS_DEBUG, "\n");
 	}
+#endif
 }
 
 static void vt8237r_enable(struct device *dev)