[coreboot] Patch set updated for coreboot: b0ab0b5 Intel Sandybridge and UMA: use mmio_resource()

[Kyösti Mälkki (kyosti.malkki@gmail.com)]

Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1373

-gerrit

commit b0ab0b5948d3452f12b071f6105add111a5c9d03
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Fri Jul 27 13:12:03 2012 +0300

    Intel Sandybridge and UMA: use mmio_resource()
    
    With SandyBridge northbridge code, uma_memory_size was reset to
    zero before variable MTRRs were set. This means MTRR setup routine
    did not previously create a un-cacheable hole for uma.
    
    Keep the behaviour that way, mmio_resource() has a prerequisuite that
    the new region does not overlap with any cacheable ram_resource().
    
    The result is not optimal setup in the number of used MTRRs, but
    continue with this approach until MTRR algorithm is improved.
    
    Change-Id: I63c8df19ad6b6350d46a3eca3055abf684b8b114
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/northbridge/intel/sandybridge/northbridge.c |   23 ++++++++++++-----------
 1 files changed, 12 insertions(+), 11 deletions(-)

diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index 0df85a7..2d948ea 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -111,17 +111,18 @@ static void add_fixed_resources(struct device *dev, int index)
 	struct resource *resource;
 	u32 pcie_config_base, pcie_config_size;
 
-	printk(BIOS_DEBUG, "Adding UMA memory area base=0x%llx "
-	       "size=0x%llx\n", uma_memory_base, uma_memory_size);
-	resource = new_resource(dev, index++);
-	resource->base = (resource_t) uma_memory_base;
-	resource->size = (resource_t) uma_memory_size;
-	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
-	    IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
-
-	/* Clear these values here so they don't get used by MTRR code */
-	uma_memory_base = 0;
-	uma_memory_size = 0;
+	/* Using uma_resource() here would fail as base & size cannot
+	 * be used as-is for a single MTRR. This would cause excessive
+	 * use of MTRRs.
+	 *
+	 * Use of mmio_resource() instead does not create UC holes by using
+	 * MTRRs, but making these regions uncacheable is taken care of by
+	 * making sure they do not overlap with any ram_resource().
+	 *
+	 * The resources can be changed to use separate mmio_resource()
+	 * calls after MTRR code is able to merge them wisely.
+	 */
+	mmio_resource(dev, index++, uma_memory_base >> 10, uma_memory_size >> 10);
 
 	if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) {
 		printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x "