[coreboot] New patch to review for coreboot: 62b6afc x86emu: Fix BSF and BSR instructions

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1360

-gerrit

commit 62b6afc5c3f8bb9bf077042b4a5fa60aaff73467
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Thu Jul 26 15:02:49 2012 -0700

    x86emu: Fix BSF and BSR instructions
    
    Patch courtesy of Michael Yaroslavtsev.
    Synced from Xorg
    http://cgit.freedesktop.org/xorg/xserver/commit/?id=66fa87292ef26bd0f464481287f3af992cd5741c
    
    Change-Id: I266f910d4a535eab4e2ad77f2540f2f1495bed61
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/devices/oprom/x86emu/ops2.c |   36 ++++++++++++++++++------------------
 1 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/src/devices/oprom/x86emu/ops2.c b/src/devices/oprom/x86emu/ops2.c
index f559874..edad6f3 100644
--- a/src/devices/oprom/x86emu/ops2.c
+++ b/src/devices/oprom/x86emu/ops2.c
@@ -1461,7 +1461,7 @@ static void x86emuOp2_bsf(u8 X86EMU_UNUSED(op2))
     uint srcoffset;
 
     START_OF_INSTR();
-    DECODE_PRINTF("BSF\n");
+    DECODE_PRINTF("BSF\t");
     FETCH_DECODE_MODRM(mod, rh, rl);
     if (mod < 3) {
         srcoffset = decode_rmXX_address(mod, rl);
@@ -1487,25 +1487,25 @@ static void x86emuOp2_bsf(u8 X86EMU_UNUSED(op2))
         }
     } else {             /* register to register */
         if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 *srcreg, *dstreg;
+            u32 srcval, *dstreg;
 
-            srcreg = DECODE_RM_LONG_REGISTER(rl);
+            srcval = *DECODE_RM_LONG_REGISTER(rl);
             DECODE_PRINTF(",");
             dstreg = DECODE_RM_LONG_REGISTER(rh);
             TRACE_AND_STEP();
-            CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF);
+            CONDITIONAL_SET_FLAG(srcval == 0, F_ZF);
             for(*dstreg = 0; *dstreg < 32; (*dstreg)++)
-                if ((*srcreg >> *dstreg) & 1) break;
+                if ((srcval >> *dstreg) & 1) break;
         } else {
-            u16 *srcreg, *dstreg;
+            u16 srcval, *dstreg;
 
-            srcreg = DECODE_RM_WORD_REGISTER(rl);
+            srcval = *DECODE_RM_WORD_REGISTER(rl);
             DECODE_PRINTF(",");
             dstreg = DECODE_RM_WORD_REGISTER(rh);
             TRACE_AND_STEP();
-            CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF);
+            CONDITIONAL_SET_FLAG(srcval == 0, F_ZF);
             for(*dstreg = 0; *dstreg < 16; (*dstreg)++)
-                if ((*srcreg >> *dstreg) & 1) break;
+                if ((srcval >> *dstreg) & 1) break;
         }
     }
     DECODE_CLEAR_SEGOVR();
@@ -1522,7 +1522,7 @@ static void x86emuOp2_bsr(u8 X86EMU_UNUSED(op2))
     uint srcoffset;
 
     START_OF_INSTR();
-    DECODE_PRINTF("BSF\n");
+    DECODE_PRINTF("BSR\t");
     FETCH_DECODE_MODRM(mod, rh, rl);
     if (mod < 3) {
         srcoffset = decode_rmXX_address(mod, rl);
@@ -1548,25 +1548,25 @@ static void x86emuOp2_bsr(u8 X86EMU_UNUSED(op2))
         }
     } else {             /* register to register */
         if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 *srcreg, *dstreg;
+            u32 srcval, *dstreg;
 
-            srcreg = DECODE_RM_LONG_REGISTER(rl);
+            srcval = *DECODE_RM_LONG_REGISTER(rl);
             DECODE_PRINTF(",");
             dstreg = DECODE_RM_LONG_REGISTER(rh);
             TRACE_AND_STEP();
-            CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF);
+            CONDITIONAL_SET_FLAG(srcval == 0, F_ZF);
             for(*dstreg = 31; *dstreg > 0; (*dstreg)--)
-                if ((*srcreg >> *dstreg) & 1) break;
+                if ((srcval >> *dstreg) & 1) break;
         } else {
-            u16 *srcreg, *dstreg;
+            u16 srcval, *dstreg;
 
-            srcreg = DECODE_RM_WORD_REGISTER(rl);
+            srcval = *DECODE_RM_WORD_REGISTER(rl);
             DECODE_PRINTF(",");
             dstreg = DECODE_RM_WORD_REGISTER(rh);
             TRACE_AND_STEP();
-            CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF);
+            CONDITIONAL_SET_FLAG(srcval == 0, F_ZF);
             for(*dstreg = 15; *dstreg > 0; (*dstreg)--)
-                if ((*srcreg >> *dstreg) & 1) break;
+                if ((srcval >> *dstreg) & 1) break;
         }
     }
     DECODE_CLEAR_SEGOVR();