[coreboot] Patch set updated for coreboot: 0a540e8 buildsystem(NOTYETREADY): Make CPU microcode updating more configurable

Alexandru Gagniuc (mr.nuke.me@gmail.com) gerrit at coreboot.org
Thu Jul 26 02:37:24 CEST 2012


Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1245

-gerrit

commit 0a540e8cb547c076c529b731150cbf09b12330da
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Fri Jul 20 00:11:21 2012 -0500

    buildsystem(NOTYETREADY): Make CPU microcode updating more configurable
    
    This patch aims to improve the microcode in CBFS handling that was
    implemented in the last patches from Stefan and the Chromium team.
    
    When the CPU selects MICROCODE_IN_CBFS, the user is given three
    choices in Kconfig
      - 1) Generate microcode from tree (default)
      - 2) Include external microcode file
      - 3) Do not put microcode in CBFS
    
    The idea is to give the user full control over including non-free
    blobs in the final ROM image.
    
    The implementation is at the moment, clumsy and disfunctional. Suggestions
    are welcome.
    
    Change-Id: I38d0c9851691aa112e93031860e94895857ebb76
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
 src/arch/x86/Makefile.inc            |   34 ++++++++++++++++----------
 src/cpu/Kconfig                      |   44 ++++++++++++++++++++++++++++++++-
 src/cpu/Makefile.inc                 |   24 ++++++++++++++++++
 src/cpu/intel/microcode/Makefile.inc |   20 ++++-----------
 src/cpu/intel/microcode/microcode.c  |    8 +++---
 src/cpu/intel/model_206ax/Kconfig    |    2 +-
 src/include/cpu/intel/microcode.h    |    2 +-
 7 files changed, 98 insertions(+), 36 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 306f239..78ecb42 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -1,3 +1,4 @@
+################################################################################
 ##
 ## This file is part of the coreboot project.
 ##
@@ -17,8 +18,8 @@
 ## along with this program; if not, write to the Free Software
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
+################################################################################
 
-#######################################################################
 # Take care of subdirectories
 subdirs-y += boot
 # subdirs-y += init
@@ -34,13 +35,20 @@ cmos_layout.bin-type = 0x01aa
 OPTION_TABLE_H:=$(obj)/option_table.h
 endif
 
-ifeq ($(CONFIG_MICROCODE_IN_CBFS),y)
-cbfs-files-y += microcode_blob.bin
-microcode_blob.bin-file = $(obj)/microcode_blob.bin
+################################################################################
+ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL), y)
+cbfs-files-y += cpu_microcode_blob.bin
+microcode_blob.bin-file = $(CONFIG_CPU_MICROCODE_FILE)
 microcode_blob.bin-type = 0x53
 endif
 
-#######################################################################
+ifeq ($(CONFIG_CPU_MICROCODE_CBFS_GENERATE), y)
+cbfs-files-y += cpu_microcode_blob.bin
+microcode_blob.bin-file = $(obj)/cpu_microcode_blob.bin
+microcode_blob.bin-type = 0x53
+endif
+
+################################################################################
 # Build the final rom image
 COREBOOT_ROM_DEPENDENCIES:=
 ifeq ($(CONFIG_PAYLOAD_ELF),y)
@@ -123,7 +131,7 @@ cbfs-files-$(CONFIG_BOOTSPLASH) += bootsplash.jpg
 bootsplash.jpg-file := $(call strip_quotes,$(CONFIG_BOOTSPLASH_FILE))
 bootsplash.jpg-type := bootsplash
 
-#######################################################################
+################################################################################
 # i386 specific tools
 NVRAMTOOL:=$(objutil)/nvramtool/nvramtool
 
@@ -135,7 +143,7 @@ $(obj)/cmos_layout.bin: $(NVRAMTOOL) $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.l
 	@printf "    OPTION     $(subst $(obj)/,,$(@))\n"
 	$(NVRAMTOOL) -y $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout -L $@
 
-#######################################################################
+################################################################################
 # Common recipes for all stages
 
 $(objcbfs)/%.bin: $(objcbfs)/%.elf
@@ -150,7 +158,7 @@ $(objcbfs)/%.elf: $(objcbfs)/%.debug
 	$(OBJCOPY) --add-gnu-debuglink=$< $@.tmp
 	mv $@.tmp $@
 
-#######################################################################
+################################################################################
 # Build the coreboot_ram (stage 2)
 
 $(objcbfs)/coreboot_ram.debug: $(objgenerated)/coreboot_ram.o $(src)/arch/x86/coreboot_ram.ld
@@ -174,7 +182,7 @@ $(objgenerated)/ramstage.a: $$(ramstage-objs)
 	rm -f $@
 	$(AR) cr $@ $^
 
-#######################################################################
+################################################################################
 # Ramstage for AP CPU (AMD K8, obsolete?)
 
 $(objcbfs)/coreboot_ap.debug: $(objgenerated)/coreboot_ap.o $(src)/arch/x86/init/ldscript_apc.lb
@@ -185,7 +193,7 @@ $(objgenerated)/coreboot_ap.o: $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c $(
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
 	$(CC) -MMD $(CFLAGS) -I$(src) -D__PRE_RAM__ -I. -I$(obj) -c $< -o $@
 
-#######################################################################
+################################################################################
 # done
 
 crt0s = $(src)/arch/x86/init/prologue.inc
@@ -264,7 +272,7 @@ ifeq ($(CONFIG_HAVE_BUS_CONFIG),y)
 ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/get_bus_conf.c
 endif
 
-#######################################################################
+################################################################################
 # Build the final rom image
 
 $(obj)/coreboot.pre: $(objcbfs)/romstage_xip.elf $(obj)/coreboot.pre1 $(CBFSTOOL)
@@ -274,7 +282,7 @@ $(obj)/coreboot.pre: $(objcbfs)/romstage_xip.elf $(obj)/coreboot.pre1 $(CBFSTOOL
 		$(CONFIG_CBFS_PREFIX)/romstage x $(shell cat $(objcbfs)/base_xip.txt)
 	mv $@.tmp $@
 
-#######################################################################
+################################################################################
 # Build the bootblock
 
 bootblock_lds = $(src)/arch/x86/init/ldscript_failover.lb
@@ -331,7 +339,7 @@ else
 	$(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/bootblock.ld $<
 endif
 
-#######################################################################
+################################################################################
 # Build the romstage
 
 $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld
diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig
index baf686e..53f978e 100644
--- a/src/cpu/Kconfig
+++ b/src/cpu/Kconfig
@@ -62,10 +62,50 @@ config SSE2
 	  streaming SIMD instructions. Some parts of coreboot can be built
 	  with more efficient code if SSE2 instructions are available.
 
-config MICROCODE_IN_CBFS
+endif # ARCH_X86
+
+config CPU_MICROCODE_IN_CBFS
 	bool "Look for microcode in CBFS"
 	default n
 	help
 	  Load microcode updates from CBFS instead of compiling them in.
 
-endif # ARCH_X86
+choice
+	prompt "Include CPU microcode in CBFS"
+	default CPU_MICROCODE_CBFS_GENERATE
+	depends on CPU_MICROCODE_IN_CBFS
+
+config CPU_MICROCODE_CBFS_GENERATE
+	bool "Generate from tree"
+	help
+	  Select this option if you want microcode updates to be assembled when
+	  building coreboot and included in the final image as a separate CBFS
+	  file. Microcode will not be hard-coded into ramstage, and may be
+	  removed from the ROM image at a later time with cbfstool.
+
+config CPU_MICROCODE_CBFS_EXTERNAL
+	depends on CPU_MICROCODE_IN_CBFS
+	bool "Include external microcode file"
+	help
+	  Select this option if you want to include an external file containing
+	  the CPU microcode. This will be included as a separate file in CBFS.
+	  A word of caution: only select this option if you are sure the
+	  microcode that you have is newer than the microcode shipping with
+	  coreboot.
+
+config CPU_MICROCODE_FILE
+	  string "Path and filename of CPU microcode"
+	  depends on CPU_MICROCODE_CBFS_EXTERNAL
+	  default "cpu_microcode.bin"
+	  help
+	    The path and filename of the file containing the CPU microcode.
+
+config CPU_MICROCODE_CBFS_NONE
+	bool "Do not include microcode updates"
+	help
+	  Select this option if you do not want CPU microcode included in CBFS.
+	  Note that for some CPUs, the microcode is hard-coded into the source
+	  tree and is not loaded from CBFS. In this case, microcode will still
+	  be updated.
+
+endchoice
diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
index 57273cf..ca39871 100644
--- a/src/cpu/Makefile.inc
+++ b/src/cpu/Makefile.inc
@@ -1,3 +1,27 @@
+################################################################################
+## Subdirectories
+################################################################################
 subdirs-y += amd
 subdirs-y += intel
 subdirs-y += via
+
+
+################################################################################
+## Rules for building the microcode blob in CBFS
+################################################################################
+
+ifeq ($(CONFIG_CPU_MICROCODE_CBFS_GENERATE),y)
+###########################
+# FIXME FIXME FIXME FIXME #
+###########################
+SRC_PATH = src/cpu/intel/
+
+FLAGS = -I $(CONFIG_MICROCODE_INCLUDE_PATH) -include $(obj)/config.h
+$(obj)/cpu_microcode_blob.o: $(SRC_PATH)/microcode_blob.c
+	$(CC) $(FLAGS) -MMD -c -o $@ $<
+
+$(obj)/cpu_microcode_blob.bin: $(obj)/cpu_microcode_blob.o
+	$(OBJCOPY) -j .data -O binary $< $@
+
+-include $(obj)/microcode_blob.d
+endif
\ No newline at end of file
diff --git a/src/cpu/intel/microcode/Makefile.inc b/src/cpu/intel/microcode/Makefile.inc
index f4d0102..22655c9 100644
--- a/src/cpu/intel/microcode/Makefile.inc
+++ b/src/cpu/intel/microcode/Makefile.inc
@@ -1,15 +1,5 @@
-ramstage-y += microcode.c
-
-
-ifeq ($(CONFIG_MICROCODE_IN_CBFS),y)
-
-SRC_PATH = src/cpu/intel/microcode
-FLAGS = -I $(CONFIG_MICROCODE_INCLUDE_PATH) -include $(obj)/config.h
-$(obj)/microcode_blob.o: $(SRC_PATH)/microcode_blob.c
-	$(CC) $(FLAGS) -MMD -c -o $@ $<
-
-$(obj)/microcode_blob.bin: $(obj)/microcode_blob.o
-	objcopy -j .data -O binary $< $@
-
--include $(obj)/microcode_blob.d
-endif
+################################################################################
+## One small file with the awesome super-power of updating the cpu microcode
+## directly from CBFS. You have been WARNED!!!
+################################################################################
+ramstage-y += microcode.c
\ No newline at end of file
diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c
index e84bad9..a4471ca 100644
--- a/src/cpu/intel/microcode/microcode.c
+++ b/src/cpu/intel/microcode/microcode.c
@@ -28,7 +28,7 @@
 #include <cpu/x86/msr.h>
 #include <cpu/intel/microcode.h>
 
-#if CONFIG_MICROCODE_IN_CBFS
+#if CONFIG_CPU_MICROCODE_IN_CBFS
 #ifdef __PRE_RAM__
 #include <arch/cbfs.h>
 #else
@@ -77,7 +77,7 @@ static inline u32 read_microcode_rev(void)
 	return msr.hi;
 }
 
-#if CONFIG_MICROCODE_IN_CBFS
+#if CONFIG_CPU_MICROCODE_IN_CBFS
 static
 #endif
 void intel_update_microcode(const void *microcode_updates)
@@ -144,9 +144,9 @@ void intel_update_microcode(const void *microcode_updates)
 	}
 }
 
-#if CONFIG_MICROCODE_IN_CBFS
+#if CONFIG_CPU_MICROCODE_IN_CBFS
 
-#define MICROCODE_CBFS_FILE "microcode_blob.bin"
+#define MICROCODE_CBFS_FILE "cpu_microcode_blob.bin"
 
 void intel_update_microcode_from_cbfs(void)
 {
diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig
index 071683e..60338e1 100644
--- a/src/cpu/intel/model_206ax/Kconfig
+++ b/src/cpu/intel/model_206ax/Kconfig
@@ -12,7 +12,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SSE2
 	select UDELAY_LAPIC
 	select SMM_TSEG
-	select MICROCODE_IN_CBFS
+	select CPU_MICROCODE_IN_CBFS
 
 config BOOTBLOCK_CPU_INIT
 	string
diff --git a/src/include/cpu/intel/microcode.h b/src/include/cpu/intel/microcode.h
index 289e919..e9c13f9 100644
--- a/src/include/cpu/intel/microcode.h
+++ b/src/include/cpu/intel/microcode.h
@@ -21,7 +21,7 @@
 #define __CPU__INTEL__MICROCODE__
 
 #ifndef __PRE_RAM__
-#if CONFIG_MICROCODE_IN_CBFS
+#if CONFIG_CPU_MICROCODE_IN_CBFS
 void intel_update_microcode_from_cbfs(void);
 #else
 void intel_update_microcode(const void *microcode_updates);




More information about the coreboot mailing list