[coreboot] Patch merged into coreboot/master: 2d3a5c5 Ivybridge: fix workaround and enable PAIR

gerrit at coreboot.org gerrit at coreboot.org
Tue Jul 24 23:51:00 CEST 2012

the following patch was just integrated into master:
commit 2d3a5c5dc15508b84883af8071870e743653a562
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Sat Jun 23 20:14:07 2012 -0700

    Ivybridge: fix workaround and enable PAIR
    MCHBAR 0x5f10[7:0] should be set to 0x30 for ivybridge
    and 0x20 for sandybridge.  Move this code to ramstage
    and set it per-chipset.
    Power Aware Interrupt Routing is supported in ivybridge,
    enable it and set fixed priority.
    Boot on ivybridge device and read MCHBAR 0x5f10:
    mmio_read8 0xfed15f10
    And verify PAIR is enabled (bit4=1):
    mmio_read8 0xfed15418
    Change-Id: If017d5ce2bd5ab5092c86f657434f2b645ee6613
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>

Build-Tested: build bot (Jenkins) at Tue Jul 24 12:22:49 2012, giving +1
Reviewed-By: Ronald G. Minnich <rminnich at gmail.com> at Tue Jul 24 23:50:20 2012, giving +2
See http://review.coreboot.org/1303 for details.


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