[coreboot] New patch to review for coreboot: f7bf0c3 Include SandyBridge Microcode when IvyBridge is enabled

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1333

-gerrit

commit f7bf0c3ba600c4ffb9a11bea6ab7b049cfe732c7
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Mon Jul 23 16:12:52 2012 -0700

    Include SandyBridge Microcode when IvyBridge is enabled
    
    .. in case the system has pluggable CPUs or might come in different SKUs.
    
    Change-Id: I7a7cd95b4de5dd78370355f448688e8d000434c1
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/cpu/intel/model_206ax/microcode_blob.h |    6 ------
 1 files changed, 0 insertions(+), 6 deletions(-)

diff --git a/src/cpu/intel/model_206ax/microcode_blob.h b/src/cpu/intel/model_206ax/microcode_blob.h
index d055b2e..66e893b 100644
--- a/src/cpu/intel/model_206ax/microcode_blob.h
+++ b/src/cpu/intel/model_206ax/microcode_blob.h
@@ -17,13 +17,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-
-#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE
 	#include "microcode-m12206a7_00000025.h"
-#elif CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE
-#else
-#error "Which microcode to use?"
-#endif
 	/*  Dummy terminator  */
         0x0, 0x0, 0x0, 0x0,
         0x0, 0x0, 0x0, 0x0,