[coreboot] New patch to review for coreboot: 9befba2 Add BAR address debug information to Oxford PCIe serial driver
Stefan Reinauer (stefan.reinauer@coreboot.org)
gerrit at coreboot.org
Tue Jul 24 01:42:23 CEST 2012
Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1327
-gerrit
commit 9befba2ae7ce00e230d563622d9460be635247b3
Author: Marc Jones <marc.jones at se-eng.com>
Date: Mon Jul 2 22:31:22 2012 -0600
Add BAR address debug information to Oxford PCIe serial driver
The Oxford PCIE Serial card has a hardcoded address at setup,
which may be moved during PCI Init. The driver re-initializes
after PCI init. Add a debug print for the new BAR address.
Initializing Oxford OXPCIe952
OXPCIe952: Class=70002 Revision ID=0
OXPCIe952: 2 UARTs detected.
OXPCIe952: Uart Bar: 0xe0800000
Change-Id: I1858d3eba09749cba3c3869060d00e621dca112a
Signed-off-by: Marc Jones <marc.jones at se-eng.com>
---
src/drivers/oxford/oxpcie/oxpcie.c | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/src/drivers/oxford/oxpcie/oxpcie.c b/src/drivers/oxford/oxpcie/oxpcie.c
index 8afdd1f..5ce4f62 100644
--- a/src/drivers/oxford/oxpcie/oxpcie.c
+++ b/src/drivers/oxford/oxpcie/oxpcie.c
@@ -38,6 +38,7 @@ static void oxford_oxpcie_enable(device_t dev)
(read32(res->base) >> 8), (read32(res->base) & 0xff));
printk(BIOS_DEBUG, "OXPCIe952: %d UARTs detected.\n",
(read32(res->base + 4) & 3));
+ printk(BIOS_DEBUG, "OXPCIe952: UART BAR: 0x%x\n", (u32)res->base);
}
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