[coreboot] New patch to review for coreboot: 0e8fa37 Add PCIe port disable debug message

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1326

-gerrit

commit 0e8fa37a7a349594407a367bf45d42d2af4a7f55
Author: Marc Jones <marc.jones at se-eng.com>
Date:   Fri Jun 15 23:03:15 2012 -0600

    Add PCIe port disable debug message
    
    The PCIe device enable function prints when it disables a device.
    The PCIe ports(bridges) use a different routine that didn't print
    the message. Add it to be consistent and to provide better debug
    output.
    
    Change-Id: I8462c48e7f4930db68703f0bfb710c01c9643a98
    Signed-off-by: Marc Jones <marc.jones at se-eng.com>
---
 src/southbridge/intel/bd82x6x/pch.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c
index 0913e1d..3c448de 100644
--- a/src/southbridge/intel/bd82x6x/pch.c
+++ b/src/southbridge/intel/bd82x6x/pch.c
@@ -297,6 +297,8 @@ static void pch_pcie_enable(device_t dev)
 	}
 
 	if (!dev->enabled) {
+		printk(BIOS_DEBUG, "%s: Disabling device\n",  dev_path(dev));
+
 		/*
 		 * PCIE Power Savings for PantherPoint and CougarPoint/B1+
 		 *