[coreboot] New patch to review for coreboot: 29b3a4c CPU: Update ivybridge PP1 current limit value

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1305

-gerrit

commit 29b3a4cf5ecef85ccfee7981427173f5b3b6edf2
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Mon Jun 25 09:53:58 2012 -0700

    CPU: Update ivybridge PP1 current limit value
    
    The BWG says ivybridge current limit for PP1 is 50A.
    
    Verify the PP1 current limit value on link device:
    
    > echo $(( ( $(rdmsr 0 0x602) & 0x1fff ) >> 3 ))
    50
    
    Change-Id: I946269d21ef605f2525fe03993f569d69128294b
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
---
 src/cpu/intel/model_206ax/model_206ax.h      |    3 ++-
 src/cpu/intel/model_206ax/model_206ax_init.c |    5 ++++-
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h
index d482ff0..fbd57a5 100644
--- a/src/cpu/intel/model_206ax/model_206ax.h
+++ b/src/cpu/intel/model_206ax/model_206ax.h
@@ -75,7 +75,8 @@
 #define MSR_PP0_CURRENT_CONFIG		0x601
 #define  PP0_CURRENT_LIMIT		(112 << 3) /* 112 A */
 #define MSR_PP1_CURRENT_CONFIG		0x602
-#define  PP1_CURRENT_LIMIT		(35 << 3) /* 35 A */
+#define  PP1_CURRENT_LIMIT_SNB		(35 << 3) /* 35 A */
+#define  PP1_CURRENT_LIMIT_IVB		(50 << 3) /* 50 A */
 #define MSR_PKG_POWER_SKU_UNIT		0x606
 #define MSR_PKG_POWER_SKU		0x614
 #define MSR_PP0_POWER_LIMIT		0x638
diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c
index 0958fe3..08757d1 100644
--- a/src/cpu/intel/model_206ax/model_206ax_init.c
+++ b/src/cpu/intel/model_206ax/model_206ax_init.c
@@ -311,7 +311,10 @@ static void configure_c_states(void)
 	/* Secondary Plane Current Limit */
 	msr = rdmsr(MSR_PP1_CURRENT_CONFIG);
 	msr.lo &= ~0x1fff;
-	msr.lo |= PP1_CURRENT_LIMIT;
+	if (cpuid_eax(1) >= 0x30600)
+		msr.lo |= PP1_CURRENT_LIMIT_IVB;
+	else
+		msr.lo |= PP1_CURRENT_LIMIT_SNB;
 	wrmsr(MSR_PP1_CURRENT_CONFIG, msr);
 }