[coreboot] New patch to review for coreboot: c1a45b1 Add support for HM70 and NM70 LPC bridge

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1300

-gerrit

commit c1a45b1d551beee81960b62025725f5436587c0c
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Thu Jun 21 16:05:21 2012 -0700

    Add support for HM70 and NM70 LPC bridge
    
    This lets the SPI driver and the LPC driver know about HM70 and NM70.
    
    Change-Id: Id2f1e0e5586a2f7200b2d24785df3f2be890da98
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/include/device/pci_ids.h                       |    2 +-
 .../intel/sandybridge/report_platform.c            |   15 +++++++++------
 src/southbridge/intel/bd82x6x/lpc.c                |   10 ++++++++++
 3 files changed, 20 insertions(+), 7 deletions(-)

diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index fd886da..7aac1f7 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -2507,7 +2507,7 @@
 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN	0x1c41
 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX	0x1c5f
 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN 0x1e41
-#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX 0x1e5d
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX 0x1e5f
 #define PCI_DEVICE_ID_INTEL_TGP_LPC	0x27bc
 
 /* Intel 82801E (C-ICH) */
diff --git a/src/northbridge/intel/sandybridge/report_platform.c b/src/northbridge/intel/sandybridge/report_platform.c
index bc88a89..ecd8f18 100644
--- a/src/northbridge/intel/sandybridge/report_platform.c
+++ b/src/northbridge/intel/sandybridge/report_platform.c
@@ -66,21 +66,24 @@ static struct {
 	const char *dev_name;
 } pch_table [] = {
 	{0x1E41, "Desktop Sample"},
+	{0x1E42, "Mobile Sample"},
+	{0x1E43, "SFF Sample"},
+	{0x1E44, "Z77"},
+	{0x1E45, "H71"},
+	{0x1E46, "Z75"},
 	{0x1E47, "Q77"},
 	{0x1E48, "Q75"},
 	{0x1E49, "B75"},
-	{0x1E44, "Z77"},
-	{0x1E46, "Z75"},
 	{0x1E4A, "H77"},
 	{0x1E53, "C216"},
-	{0x1E42, "Mobile Sample"},
 	{0x1E55, "QM77"},
+	{0x1E56, "QS77"},
 	{0x1E58, "UM77"},
 	{0x1E57, "HM77"},
 	{0x1E59, "HM76"},
-	{0x1E5d, "HM75"},
-	{0x1E43, "SFF Sample"},
-	{0x1E56, "QS77"},
+	{0x1E5D, "HM75"},
+	{0x1E5E, "HM70"},
+	{0x1E5F, "NM70"},
 };
 
 static void report_pch_info(void)
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index dddab6a..703fc8a 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -684,3 +684,13 @@ static const struct pci_driver hm75_lpc __pci_driver = {
 	.vendor	= PCI_VENDOR_ID_INTEL,
 	.device	= 0x1e5d,
 };
+static const struct pci_driver hm70_lpc __pci_driver = {
+	.ops	= &device_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x1e5e,
+};
+static const struct pci_driver nm70_lpc __pci_driver = {
+	.ops	= &device_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x1e5f,
+};