[coreboot] Patch merged into coreboot/master: b8b5b1e AMD: Fix GFXUMA with 4GB or more RAM

gerrit at coreboot.org gerrit at coreboot.org
Mon Jul 16 18:57:45 CEST 2012

the following patch was just integrated into master:
commit b8b5b1e535becc2ff11767dced0d2a875e4b763e
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Tue Jul 10 13:10:24 2012 +0300

    AMD: Fix GFXUMA with 4GB or more RAM
    Northbridge code incorrectly adjusted the last cacheable memory
    resource to accomodate room for UMA framebuffer. If system had
    4GB or more memory that last resource is not below 4GB and not
    the one where UMA is located.
    There are three consequences:
    The last entry in coreboot memory table is reduced by uma_memory_size.
    Due the incorrect code in northbridge code state.tomk,
    end of last resource below 4GB, had not been adjusted.
    Incrementing that by uma_memory_size diverts a region
    possibly claimed for MMIO to RAM, as TOP_MEM is written.
    Since the UMA framebuffer did not have IORESOURCE_CACHEABLE,
    it was ignored from the MTRR setup and not set uncacheable.
    The setting of TOP_MEM and TOP_MEM2, as well as all the MTRRs,
    should be copied from BSP to all APs instead of deriving the data
    separately for each Logical CPU.
    Change-Id: I8e69fc8854b776fe9e4fe6ddfb101eba14888939
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>

Reviewed-By: Patrick Georgi <patrick at georgi-clan.de> at Mon Jul 16 18:57:43 2012, giving +2
See http://review.coreboot.org/1217 for details.


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