[coreboot] New patch to review for coreboot: c2f9141 Supermicro X7DB8: Use autogeneration of mptable
Sven Schnelle (svens@stackframe.org)
gerrit at coreboot.org
Fri Jul 13 10:21:50 CEST 2012
Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1222
-gerrit
commit c2f9141eee1fdd4108ed5f072610f8d96317dd14
Author: Sven Schnelle <svens at stackframe.org>
Date: Mon Jun 25 21:35:45 2012 +0200
Supermicro X7DB8: Use autogeneration of mptable
And fix the wrong indenting of devicetree.cb while at it.
Change-Id: Idbb19fb5d7155f44675098e79920caf65191c239
Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
src/mainboard/supermicro/x7db8/Kconfig | 1 +
src/mainboard/supermicro/x7db8/devicetree.cb | 184 ++++++++++++++++----------
2 files changed, 115 insertions(+), 70 deletions(-)
diff --git a/src/mainboard/supermicro/x7db8/Kconfig b/src/mainboard/supermicro/x7db8/Kconfig
index 5365f85..2e26c78 100644
--- a/src/mainboard/supermicro/x7db8/Kconfig
+++ b/src/mainboard/supermicro/x7db8/Kconfig
@@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_MP_TABLE
select HAVE_PIRQ_TABLE
select DRIVERS_I2C_W83793
+ select DRIVERS_GENERIC_IOAPIC
config MAINBOARD_DIR
string
diff --git a/src/mainboard/supermicro/x7db8/devicetree.cb b/src/mainboard/supermicro/x7db8/devicetree.cb
index 66e5cfe..8949c54 100644
--- a/src/mainboard/supermicro/x7db8/devicetree.cb
+++ b/src/mainboard/supermicro/x7db8/devicetree.cb
@@ -33,22 +33,30 @@ chip northbridge/intel/i5000
subsystemid 0x15d9 0x2017
end
- device pci 02.0 on # PCIe bridge
- device pci 00.0 on
- device pci 00.0 on
- device pci 00.0 on end
- device pci 02.0 on end
- end
- device pci 02.0 on
- device pci 00.0 on
- device pci 02.0 on
- device pci 00.0 on end # e1000 #1
- device pci 00.1 on end # e1000 #2
+ device pci 02.0 on # PCI Express x8 Port 2-3
+ ioapic_irq 8 INTA 0x10
+ ioapic_irq 8 INTB 0x11
+ ioapic_irq 8 INTC 0x12
+ ioapic_irq 8 INTD 0x13
+ device pci 00.0 on # PCI Express Upstream Port
+ device pci 00.0 on # PCI Express Downstream Port E1
+ device pci 00.0 on # 6700PXH PCI Express-to-PCI Bridge A
+ ioapic_irq 8 INTA 0x11
+ ioapic_irq 8 INTB 0x10
+ ioapic_irq 8 INTC 0x11
+ ioapic_irq 8 INTD 0x10
+ # PCI slot
+ device pci 00.2 on # 6700PXH PCI Express-to-PCI Bridge B
+ # PCI slot
+ end
+ device pci 02.0 on # Adaptec U320 #1
+ ioapic_irq 8 INTA 0x10
+ end
+ device pci 02.1 on # Adaptec U320 #2
+ ioapic_irq 8 INTB 0x11
end
end
- device pci 00.1 on end
end
- end
device pci 00.1 on end
device pci 00.3 on end
end
@@ -58,6 +66,31 @@ chip northbridge/intel/i5000
device pci 05.0 on end
device pci 06.0 on end
device pci 07.0 on end
+ device pci 00.3 on # PCI Express to PCI-X Bridge
+ ioapic_irq 9 INTA 3
+ ioapic_irq 9 INTB 0
+ ioapic_irq 9 INTC 1
+ ioapic_irq 9 INTD 2
+ # PCI-X Slot
+ end
+ end
+
+ device pci 03.0 on
+ ioapic_irq 8 INTA 0x10
+ end
+ device pci 04.0 on
+ ioapic_irq 8 INTA 0x10
+ end
+ device pci 05.0 on
+ ioapic_irq 8 INTA 0x10
+ end
+ device pci 06.0 on
+ ioapic_irq 8 INTA 0x10
+ end
+ device pci 07.0 on
+ ioapic_irq 8 INTA 0x10
+ end
+
device pci 10.0 on end # FBD
device pci 10.1 on end # FBD
device pci 10.2 on end # FBD
@@ -71,68 +104,79 @@ chip northbridge/intel/i5000
register "pirq_e_h" = "0x80808080"
register "sata_ports_implemented" = "0x3f"
- device pci 1c.0 on end # PCIe bridge
- device pci 1d.0 on end # USB UHCI
- device pci 1d.1 on end # USB UHCI
- device pci 1d.2 on end # USB UHCI
- device pci 1d.3 on end # USB UHCI
- device pci 1d.7 on end # USB2 EHCI
- device pci 1e.0 on
- device pci 01.0 on
- end
- end
+ device pci 1c.0 on
+ ioapic_irq 8 INTA 0x14
+ ioapic_irq 8 INTB 0x15
+ ioapic_irq 8 INTC 0x16
+ ioapic_irq 8 INTD 0x17
+ end # PCIe bridge
+ device pci 1d.0 on
+ ioapic_irq 8 INTA 0x10
+ end # USB UHCI
+ device pci 1d.1 on
+ ioapic_irq 8 INTB 0x11
+ end # USB UHCI
+ device pci 1d.2 on
+ ioapic_irq 8 INTC 0x12
+ end # USB UHCI
+ device pci 1d.3 on
+ ioapic_irq 8 INTD 0x13
+ end # USB UHCI
+ device pci 1d.7 on end # USB2 EHCI
+ device pci 1e.0 on
+ device pci 01.0 on end
+ end
- device pci 1f.0 on # PCI-LPC bridge
- subsystemid 0x15d9 0x2009
- chip superio/winbond/w83627hf
- device pnp 2e.0 off end # FDC
- device pnp 2e.1 on # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.2 on # Serial Port 1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
+ device pci 1f.0 on # PCI-LPC bridge
+ ioapic_irq 8 INTA 0x11
+ subsystemid 0x15d9 0x2009
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 off end # FDC
+ device pnp 2e.1 on # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Serial Port 1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
- device pnp 2e.3 off end
- device pnp 2e.5 on # KBC
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 12
+ device pnp 2e.3 off end
+ device pnp 2e.5 on # KBC
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off end # CIR
+ device pnp 2e.7 off end # Game port / MIDI
+ device pnp 2e.8 off end # GPIO2
+ device pnp 2e.9 on end # GPIO3
+ device pnp 2e.a on end # ACPI
+ device pnp 2e.b off end # HWMON
end
-
- device pnp 2e.6 off end # CIR
- device pnp 2e.7 off end # Game port / MIDI
- device pnp 2e.8 off end # GPIO2
- device pnp 2e.9 on end # GPIO3
- device pnp 2e.a on end # ACPI
- device pnp 2e.b off end # HWMON
- end
- end
- device pci 1f.1 off end # IDE
- device pci 1f.2 on end # SATA
- device pci 1f.3 on
- chip drivers/i2c/w83793
- register "mfc" = "0x28"
- register "fanin" = "0x1f"
- register "peci_agent_conf" = "0x33"
- register "tcase0" = "0x5e"
- register "tcase1" = "0x5e"
- register "tcase2" = "0x5e"
- register "tcase3" = "0x5e"
- register "tr_enable" = "0x01"
- register "critical_temperature" = "0x7f"
- register "td1_fan_select" = "0x01"
- register "td2_fan_select" = "0x01"
- register "td3_fan_select" = "0x01"
- register "td4_fan_select" = "0x01"
-
- device i2c 0x2f on end
end
- end # SMBUS
+ device pci 1f.1 off end # IDE
+ device pci 1f.2 on end # SATA
+ device pci 1f.3 on
+ chip drivers/i2c/w83793
+ register "mfc" = "0x28"
+ register "fanin" = "0x1f"
+ register "peci_agent_conf" = "0x33"
+ register "tcase0" = "0x5e"
+ register "tcase1" = "0x5e"
+ register "tcase2" = "0x5e"
+ register "tcase3" = "0x5e"
+ register "tr_enable" = "0x01"
+ register "critical_temperature" = "0x7f"
+ register "td1_fan_select" = "0x01"
+ register "td2_fan_select" = "0x01"
+ register "td3_fan_select" = "0x01"
+ register "td4_fan_select" = "0x01"
+ device i2c 0x2f on end
+ end
+ end # SMBUS
end
end
end
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