[coreboot] Patch set updated for coreboot: c95120c AMD northbridges: drop APIC allocation in bus_scan

Kyösti Mälkki (kyosti.malkki@gmail.com) gerrit at coreboot.org
Tue Jul 10 09:50:46 CEST 2012


Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1186

-gerrit

commit c95120cda47555e17b2caaef4b747bdddaa7031b
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Fri Jul 6 19:02:56 2012 +0300

    AMD northbridges: drop APIC allocation in bus_scan
    
    Allocation will take place for every CPU responding to Broadcast
    SIPI at a later time in cpu_initialize().
    
    Change-Id: I153dc1a5cab4f2eae4ab3a57af02841cb1a261c0
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/northbridge/amd/agesa/family10/northbridge.c   |   59 +-------------------
 src/northbridge/amd/agesa/family14/northbridge.c   |   21 +------
 src/northbridge/amd/agesa/family15/northbridge.c   |   53 ------------------
 src/northbridge/amd/agesa/family15tn/northbridge.c |   56 +------------------
 src/northbridge/amd/amdfam10/northbridge.c         |   53 +-----------------
 src/northbridge/amd/amdk8/northbridge.c            |   54 +------------------
 6 files changed, 6 insertions(+), 290 deletions(-)

diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c
index 8d4c334..aafe001 100644
--- a/src/northbridge/amd/agesa/family10/northbridge.c
+++ b/src/northbridge/amd/agesa/family10/northbridge.c
@@ -1327,8 +1327,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
 	/* Find which cpus are present */
 	cpu_bus = dev->link_list;
 	for (i = 0; i < nodes; i++) {
-		device_t cdb_dev, cpu;
-		struct device_path cpu_path;
+		device_t cdb_dev;
 		unsigned busn, devn;
 		struct bus *pbus;
 
@@ -1379,62 +1378,6 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
 			printk(BIOS_DEBUG, "  %s siblings=%d\n", dev_path(cdb_dev), cores_found);
 		}
 
-		u32 jj;
-		if (disable_siblings) {
-			jj = 0;
-		} else {
-			jj = cores_found;
-		}
-
-		for (j = 0; j <=jj; j++ ) {
-			extern CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration;
-			u32 modules = TopologyConfiguration.PlatformNumberOfModules;
-			u32 lapicid_start = 0;
-
-			/* Build the cpu device path */
-			cpu_path.type = DEVICE_PATH_APIC;
-			/*
-			 * APIC ID calucation is tightly coupled with AGESA v5 code.
-			 * This calculation MUST match the assignment calculation done
-			 * in LocalApicInitializationAtEarly() function.
-			 * And reference GetLocalApicIdForCore()
-			 *
-			 * Apply apic enumeration rules
-			 * For systems with >= 16 APICs, put the IO-APICs at 0..n and
-			 * put the local-APICs at m..z
-			 * For systems with < 16 APICs, put the Local-APICs at 0..n and
-			 * put the IO-APICs at (n + 1)..z
-			 */
-			if (nodes * (cores_found + 1) >= 0x10) {
-  				lapicid_start = 0x10;
-			}
-			cpu_path.apic.apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (cores_found + 1)) : j);
-
-			/* See if I can find the cpu */
-			cpu = find_dev_path(cpu_bus, &cpu_path);
-
-			/* Enable the cpu if I have the processor */
-			if (cdb_dev && cdb_dev->enabled) {
-				if (!cpu) {
-					cpu = alloc_dev(cpu_bus, &cpu_path);
-				}
-				if (cpu) {
-					cpu->enabled = 1;
-				}
-			}
-
-			/* Disable the cpu if I don't have the processor */
-			if (cpu && (!cdb_dev || !cdb_dev->enabled)) {
-				cpu->enabled = 0;
-			}
-
-			/* Report what I have done */
-			if (cpu) {
-				printk(BIOS_DEBUG, "CPU: %s %s\n",
-					dev_path(cpu), cpu->enabled?"enabled":"disabled");
-			}
-
-		} //j
 	}
 	return max;
 }
diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c
index 7f6b6f7..7ed53f2 100644
--- a/src/northbridge/amd/agesa/family14/northbridge.c
+++ b/src/northbridge/amd/agesa/family14/northbridge.c
@@ -816,31 +816,14 @@ static void cpu_bus_set_resources(device_t dev) {
 
 static u32 cpu_bus_scan(device_t dev, u32 max)
 {
-	device_t cpu;
-	struct device_path cpu_path;
-	int apic_id, cores_found;
+	int cores_found;
 
 	/* There is only one node for fam14, but there may be multiple cores. */
-	cpu = dev_find_slot(0, PCI_DEVFN(0x18, 0));
-	if (!cpu)
+	if (! dev_find_slot(0, PCI_DEVFN(0x18, 0)))
 		printk(BIOS_ERR, "ERROR: %02x:%02x.0 not found", 0, 0x18);
 
 	cores_found = (pci_read_config32(dev_find_slot(0,PCI_DEVFN(0x18,0x3)), 0xe8) >> 12) & 3;
 	printk(BIOS_DEBUG, "  AP siblings=%d\n", cores_found);
-
-
-	for (apic_id = 0; apic_id <= cores_found; apic_id++) {
-		cpu_path.type = DEVICE_PATH_APIC;
-		cpu_path.apic.apic_id = apic_id;
-		cpu = alloc_find_dev(dev->link_list, &cpu_path);
-		if (cpu) {
-			cpu->enabled = 1;
-			printk(BIOS_DEBUG, "CPU: %s %s\n",
-					dev_path(cpu), cpu->enabled?"enabled":"disabled");
-		} else {
-			cpu->enabled = 0;
-		}
-	}
 	return max;
 }
 
diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c
index 5951154..387d91d 100644
--- a/src/northbridge/amd/agesa/family15/northbridge.c
+++ b/src/northbridge/amd/agesa/family15/northbridge.c
@@ -1034,59 +1034,6 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
 		printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n",
 				dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings);
 
-		for (j = 0; j <= siblings; j++ ) {
-			extern CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration;
-			u32 modules = TopologyConfiguration.PlatformNumberOfModules;
-			u32 lapicid_start = 0;
-
-			/* Build the cpu device path */
-			cpu_path.type = DEVICE_PATH_APIC;
-			/*
-			 * APIC ID calucation is tightly coupled with AGESA v5 code.
-			 * This calculation MUST match the assignment calculation done
-			 * in LocalApicInitializationAtEarly() function.
-			 * And reference GetLocalApicIdForCore()
-			 *
-			 * Apply apic enumeration rules
-			 * For systems with >= 16 APICs, put the IO-APICs at 0..n and
-			 * put the local-APICs at m..z
-			 *
-			 * This is needed because many IO-APIC devices only have 4 bits
-			 * for their APIC id and therefore must reside at 0..15
-                         */
-#ifndef CFG_PLAT_NUM_IO_APICS /* defined in mainboard buildOpts.c */
-#define CFG_PLAT_NUM_IO_APICS 3
-#endif
-			if ((node_nums * core_max) + CFG_PLAT_NUM_IO_APICS >= 0x10) {
-				lapicid_start = (CFG_PLAT_NUM_IO_APICS - 1) / core_max;
-				lapicid_start = (lapicid_start + 1) * core_max;
-				printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start);
-			}
-			cpu_path.apic.apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j);
-			printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n",
-					i, j, cpu_path.apic.apic_id);
-
-			/* See if I can find the cpu */
-			cpu = find_dev_path(cpu_bus, &cpu_path);
-			/* Enable the cpu if I have the processor */
-			if (cdb_dev && cdb_dev->enabled) {
-				if (!cpu) {
-					cpu = alloc_dev(cpu_bus, &cpu_path);
-				}
-				if (cpu) {
-					cpu->enabled = 1;
-				}
-			}
-			/* Disable the cpu if I don't have the processor */
-			if (cpu && (!cdb_dev || !cdb_dev->enabled)) {
-				cpu->enabled = 0;
-			}
-			/* Report what I have done */
-			if (cpu) {
-				printk(BIOS_DEBUG, "CPU: %s %s\n",
-					dev_path(cpu), cpu->enabled?"enabled":"disabled");
-			}
-		} //j
 	}
 	return max;
 }
diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c
index bd63b67..25ad08e 100644
--- a/src/northbridge/amd/agesa/family15tn/northbridge.c
+++ b/src/northbridge/amd/agesa/family15tn/northbridge.c
@@ -958,8 +958,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
 	/* Find which cpus are present */
 	cpu_bus = dev->link_list;
 	for (i = 0; i < node_nums; i++) {
-		device_t cdb_dev, cpu;
-		struct device_path cpu_path;
+		device_t cdb_dev;
 		unsigned busn, devn;
 		struct bus *pbus;
 
@@ -1018,59 +1017,6 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
 		printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n",
 				dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings);
 
-		for (j = 0; j <= siblings; j++ ) {
-			extern CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration;
-			u32 modules = TopologyConfiguration.PlatformNumberOfModules;
-			u32 lapicid_start = 0;
-
-			/* Build the cpu device path */
-			cpu_path.type = DEVICE_PATH_APIC;
-			/*
-			 * APIC ID calucation is tightly coupled with AGESA v5 code.
-			 * This calculation MUST match the assignment calculation done
-			 * in LocalApicInitializationAtEarly() function.
-			 * And reference GetLocalApicIdForCore()
-			 *
-			 * Apply apic enumeration rules
-			 * For systems with >= 16 APICs, put the IO-APICs at 0..n and
-			 * put the local-APICs at m..z
-			 *
-			 * This is needed because many IO-APIC devices only have 4 bits
-			 * for their APIC id and therefore must reside at 0..15
-                         */
-#ifndef CFG_PLAT_NUM_IO_APICS /* defined in mainboard buildOpts.c */
-#define CFG_PLAT_NUM_IO_APICS 3
-#endif
-			if ((node_nums * core_max) + CFG_PLAT_NUM_IO_APICS >= 0x10) {
-				lapicid_start = (CFG_PLAT_NUM_IO_APICS - 1) / core_max;
-				lapicid_start = (lapicid_start + 1) * core_max;
-				printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start);
-			}
-			cpu_path.apic.apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j);
-			printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n",
-					i, j, cpu_path.apic.apic_id);
-
-			/* See if I can find the cpu */
-			cpu = find_dev_path(cpu_bus, &cpu_path);
-			/* Enable the cpu if I have the processor */
-			if (cdb_dev && cdb_dev->enabled) {
-				if (!cpu) {
-					cpu = alloc_dev(cpu_bus, &cpu_path);
-				}
-				if (cpu) {
-					cpu->enabled = 1;
-				}
-			}
-			/* Disable the cpu if I don't have the processor */
-			if (cpu && (!cdb_dev || !cdb_dev->enabled)) {
-				cpu->enabled = 0;
-			}
-			/* Report what I have done */
-			if (cpu) {
-				printk(BIOS_DEBUG, "CPU: %s %s\n",
-					dev_path(cpu), cpu->enabled?"enabled":"disabled");
-			}
-		} //j
 	}
 	return max;
 }
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index e5ba5ea..0079e06 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -1338,8 +1338,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
 	/* Find which cpus are present */
 	cpu_bus = dev->link_list;
 	for(i = 0; i < nodes; i++) {
-		device_t cdb_dev, cpu;
-		struct device_path cpu_path;
+		device_t cdb_dev;
 		unsigned busn, devn;
 		struct bus *pbus;
 
@@ -1390,56 +1389,6 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
 			printk(BIOS_DEBUG, "  %s siblings=%d\n", dev_path(cdb_dev), cores_found);
 		}
 
-		u32 jj;
-		if(disable_siblings) {
-			jj = 0;
-		} else
-		{
-			jj = cores_found;
-		}
-
-		for (j = 0; j <=jj; j++ ) {
-
-			/* Build the cpu device path */
-			cpu_path.type = DEVICE_PATH_APIC;
-			cpu_path.apic.apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:64); // ?
-
-			/* See if I can find the cpu */
-			cpu = find_dev_path(cpu_bus, &cpu_path);
-
-			/* Enable the cpu if I have the processor */
-			if (cdb_dev && cdb_dev->enabled) {
-				if (!cpu) {
-					cpu = alloc_dev(cpu_bus, &cpu_path);
-				}
-				if (cpu) {
-					cpu->enabled = 1;
-				}
-			}
-
-			/* Disable the cpu if I don't have the processor */
-			if (cpu && (!cdb_dev || !cdb_dev->enabled)) {
-				cpu->enabled = 0;
-			}
-
-			/* Report what I have done */
-			if (cpu) {
-	#if CONFIG_ENABLE_APIC_EXT_ID && (CONFIG_APIC_ID_OFFSET>0)
-				if(sysconf.enabled_apic_ext_id) {
-					if(sysconf.lift_bsp_apicid) {
-						cpu->path.apic.apic_id += sysconf.apicid_offset;
-					} else
-					{
-						if (cpu->path.apic.apic_id != 0)
-							cpu->path.apic.apic_id += sysconf.apicid_offset;
-					}
-				}
-	#endif
-				printk(BIOS_DEBUG, "CPU: %s %s\n",
-					dev_path(cpu), cpu->enabled?"enabled":"disabled");
-			}
-
-		} //j
 	}
 	return max;
 }
diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c
index fba0e04..30ed1f9 100644
--- a/src/northbridge/amd/amdk8/northbridge.c
+++ b/src/northbridge/amd/amdk8/northbridge.c
@@ -1211,8 +1211,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
 	/* Find which cpus are present */
 	cpu_bus = dev->link_list;
 	for(i = 0; i < sysconf.nodes; i++) {
-		device_t cpu_dev, cpu;
-		struct device_path cpu_path;
+		device_t cpu_dev;
 
 		/* Find the cpu's pci device */
 		cpu_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3));
@@ -1271,57 +1270,6 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
   			}
 		}
 
-		u32 jj;
-		if(e0_later_single_core || disable_siblings) {
-			jj = 0;
-		} else
-		{
-			jj = siblings;
-		}
-#if 0
-		jj = 0; // if create cpu core1 path in amd_siblings by core0
-#endif
-
-		for (j = 0; j <=jj; j++ ) {
-
-			/* Build the cpu device path */
-			cpu_path.type = DEVICE_PATH_APIC;
-			cpu_path.apic.apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:8);
-
-			/* See if I can find the cpu */
-			cpu = find_dev_path(cpu_bus, &cpu_path);
-
-			/* Enable the cpu if I have the processor */
-			if (cpu_dev && cpu_dev->enabled) {
-				if (!cpu) {
-					cpu = alloc_dev(cpu_bus, &cpu_path);
-				}
-				if (cpu) {
-					cpu->enabled = 1;
-				}
-			}
-
-			/* Disable the cpu if I don't have the processor */
-			if (cpu && (!cpu_dev || !cpu_dev->enabled)) {
-				cpu->enabled = 0;
-			}
-
-			/* Report what I have done */
-			if (cpu) {
-				if(sysconf.enabled_apic_ext_id) {
-					if(sysconf.lift_bsp_apicid) {
-						cpu->path.apic.apic_id += sysconf.apicid_offset;
-					} else
-					{
-						if (cpu->path.apic.apic_id != 0)
-							cpu->path.apic.apic_id += sysconf.apicid_offset;
-					}
-				}
-				printk(BIOS_DEBUG, "CPU: %s %s\n",
-					dev_path(cpu), cpu->enabled?"enabled":"disabled");
-			}
-
-		} //j
 	}
 	return max;
 }




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