[coreboot] Patch set updated for coreboot: 0e08243 Auto-generate bootblock initialisation
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Thu Feb 23 13:20:03 CET 2012
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/473
-gerrit
commit 0e0824334189ff17f31d211c5488b86206c61035
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Thu Feb 23 14:17:53 2012 +0200
Auto-generate bootblock initialisation
The following chip-specific functions were renamed to include
chip name in the function:
- bootblock_northbridge_init
- bootblock_southbridge_init
The following no-operation bootblock.c files were removed:
- northbridge/amd/agesa/family10/bootblock.c
- northbridge/amd/agesa/family12/bootblock.c
- northbridge/amd/agesa/family14/bootblock.c
- northbridge/amd/agesa/family15/bootblock.c
A new init function called from bootblock is declared as:
- unsigned long init_mainboard(int bsp_cpu)
For BSP CPU bootblock calls init_mainboard(true). For AP CPUs bootblock
calls init_mainboard(false). Usually AP CPU has nothing to do here.
By default, build toolchain creates and includes an init_mainboard()
function in file build/mainboard/x/x/bootblock_autogen.h that executes
init functions from any bootblock.c files for all chips listed in
mainboard/devtree.cb.
Alternatively a mainboard/x/x/bootblock.c file is added in the
bootblock build, if a Kconfig option HAS_MAINBOARD_BOOTBLOCK is set.
One should copy the auto-generated init_mainboard() to this file,
and optionally read various bootstrap signals or status bits from
super-io and southbridge component to gain some control over the
selection of romstage to boot via the return value.
Samples of such (yet not implemented) controls for boot behaviour:
- Reset CMOS to defaults on user request (jumper).
- Use fallback prefix after power-button 4s override.
- Refuse boot after intruder detection.
- On remote wakeup, request network boot.
Change-Id: Ib1d101cdd68993530c9c7a653ac000a01de52ac2
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/arch/x86/Kconfig | 7 +----
src/arch/x86/Makefile.inc | 9 +++++-
src/arch/x86/include/bootblock_common.h | 17 +-------------
src/arch/x86/init/bootblock_normal.c | 8 +++---
src/arch/x86/init/bootblock_simple.c | 10 ++++----
src/mainboard/hp/dl165_g6_fam10/Kconfig | 5 +---
src/mainboard/hp/dl165_g6_fam10/bootblock.c | 10 +++++++-
src/northbridge/amd/agesa/family10/Kconfig | 3 --
src/northbridge/amd/agesa/family10/bootblock.c | 29 ------------------------
src/northbridge/amd/agesa/family12/Kconfig | 4 ---
src/northbridge/amd/agesa/family12/bootblock.c | 29 ------------------------
src/northbridge/amd/agesa/family14/Kconfig | 4 ---
src/northbridge/amd/agesa/family14/bootblock.c | 29 ------------------------
src/northbridge/amd/agesa/family15/Kconfig | 3 --
src/northbridge/amd/agesa/family15/bootblock.c | 25 --------------------
src/northbridge/amd/amdfam10/Kconfig | 4 ---
src/northbridge/amd/amdfam10/bootblock.c | 2 +-
src/northbridge/amd/amdk8/Kconfig | 4 ---
src/northbridge/amd/amdk8/bootblock.c | 2 +-
src/southbridge/amd/amd8111/Kconfig | 4 ---
src/southbridge/amd/amd8111/bootblock.c | 2 +-
src/southbridge/amd/cimx/sb700/Kconfig | 3 --
src/southbridge/amd/cimx/sb700/bootblock.c | 2 +-
src/southbridge/amd/cimx/sb800/Kconfig | 3 --
src/southbridge/amd/cimx/sb800/bootblock.c | 2 +-
src/southbridge/amd/cimx/sb900/Kconfig | 3 --
src/southbridge/amd/cimx/sb900/bootblock.c | 2 +-
src/southbridge/amd/sb600/Kconfig | 3 --
src/southbridge/amd/sb600/bootblock.c | 2 +-
src/southbridge/amd/sb700/Kconfig | 5 ----
src/southbridge/amd/sb700/bootblock.c | 2 +-
src/southbridge/amd/sb800/Kconfig | 5 ----
src/southbridge/amd/sb800/bootblock.c | 2 +-
src/southbridge/broadcom/bcm5785/Kconfig | 4 ---
src/southbridge/broadcom/bcm5785/bootblock.c | 2 +-
src/southbridge/intel/i82371eb/Kconfig | 5 ----
src/southbridge/intel/i82371eb/bootblock.c | 2 +-
src/southbridge/intel/i82801gx/Kconfig | 5 ----
src/southbridge/intel/i82801gx/bootblock.c | 2 +-
src/southbridge/nvidia/ck804/Kconfig | 6 ++--
src/southbridge/nvidia/ck804/bootblock.c | 2 +-
src/southbridge/nvidia/mcp55/Kconfig | 6 ++--
src/southbridge/nvidia/mcp55/bootblock.c | 2 +-
src/southbridge/sis/sis966/Kconfig | 7 +++--
src/southbridge/sis/sis966/bootblock.c | 2 +-
src/southbridge/via/vt8237r/Kconfig | 4 ---
src/southbridge/via/vt8237r/bootblock.c | 2 +-
47 files changed, 55 insertions(+), 240 deletions(-)
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index e71d0f3..07ad95f 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -67,8 +67,8 @@ config PC80_SYSTEM
bool
default y
-config BOOTBLOCK_NORTHBRIDGE_INIT
- string
+config HAS_MAINBOARD_BOOTBLOCK
+ def_bool n
config HAVE_CMOS_DEFAULT
def_bool n
@@ -77,9 +77,6 @@ config CMOS_DEFAULT_FILE
string
depends on HAVE_CMOS_DEFAULT
-config BOOTBLOCK_SOUTHBRIDGE_INIT
- string
-
config BIG_ENDIAN
bool
default n
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 624b510..e1a9f6d 100755
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -324,11 +324,16 @@ $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.s: $(obj)/bootblock/bootblock.S $(obj
@printf " CC $(subst $(obj)/,,$(@))\n"
$(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/bootblock -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@
-$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc: $(src)/arch/x86/init/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H)
+$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc: $(src)/arch/x86/init/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(obj)/mainboard/$(MAINBOARDDIR)/bootblock_autogen.h $(objutil)/romcc/romcc $(OPTION_TABLE_H)
@printf " ROMCC $(subst $(obj)/,,$(@))\n"
$(CC) -MM -MT$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc \
$< > $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc.d
- $(ROMCC) -c -S $(bootblock_romccflags) $(ROMCCFLAGS) -I. $(INCLUDES) $< -o $@
+ $(ROMCC) -c -S $(bootblock_romccflags) $(ROMCCFLAGS) -I. $(INCLUDES) -I$(@D) $< -o $@
+
+$(obj)/mainboard/$(MAINBOARDDIR)/bootblock_autogen.h: $(src)/mainboard/$(MAINBOARDDIR)/devicetree.cb $(objutil)/sconfig/sconfig
+ @printf " SCONFIG $(subst $(src)/,,$(<)) (bootblock)\n"
+ mkdir -p $(@D)
+ $(objutil)/sconfig/sconfig $(MAINBOARDDIR) $(@D) -b $(@F)
$(obj)/bootblock.elf: $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.o $(obj)/bootblock/ldscript.ld
@printf " LINK $(subst $(obj)/,,$(@))\n"
diff --git a/src/arch/x86/include/bootblock_common.h b/src/arch/x86/include/bootblock_common.h
index bd19682..69ab22c 100644
--- a/src/arch/x86/include/bootblock_common.h
+++ b/src/arch/x86/include/bootblock_common.h
@@ -1,22 +1,7 @@
#include <cpu/x86/lapic/boot_cpu.c>
-#ifdef CONFIG_BOOTBLOCK_CPU_INIT
-#include CONFIG_BOOTBLOCK_CPU_INIT
-#else
-static void bootblock_cpu_init(void) { }
-#endif
-#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT
-#include CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT
-#else
-static void bootblock_northbridge_init(void) { }
-#endif
-#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT
-#include CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT
-#else
-static void bootblock_southbridge_init(void) { }
-#endif
-
#include <arch/cbfs.h>
+#include "bootblock_autogen.h"
#if CONFIG_USE_OPTION_TABLE
#include <pc80/mc146818rtc.h>
diff --git a/src/arch/x86/init/bootblock_normal.c b/src/arch/x86/init/bootblock_normal.c
index f8ae13b..48b4131 100644
--- a/src/arch/x86/init/bootblock_normal.c
+++ b/src/arch/x86/init/bootblock_normal.c
@@ -4,13 +4,13 @@
static void main(unsigned long bist)
{
unsigned long entry;
+ int bsp_cpu = boot_cpu();
int boot_mode;
- if (boot_cpu()) {
- bootblock_northbridge_init();
- bootblock_southbridge_init();
- bootblock_cpu_init();
+ /* Mainboard-specific early init. */
+ init_mainboard(bsp_cpu);
+ if (bsp_cpu) {
#if CONFIG_USE_OPTION_TABLE
sanitize_cmos();
#endif
diff --git a/src/arch/x86/init/bootblock_simple.c b/src/arch/x86/init/bootblock_simple.c
index 41f73b4..f4e4bbf 100644
--- a/src/arch/x86/init/bootblock_simple.c
+++ b/src/arch/x86/init/bootblock_simple.c
@@ -2,15 +2,15 @@
static void main(unsigned long bist)
{
- if (boot_cpu()) {
- bootblock_northbridge_init();
- bootblock_southbridge_init();
- bootblock_cpu_init();
+ int bsp_cpu = boot_cpu();
+
+ /* Mainboard-specific early init. */
+ init_mainboard(bsp_cpu);
#if CONFIG_USE_OPTION_TABLE
+ if (bsp_cpu)
sanitize_cmos();
#endif
- }
const char* target1 = "fallback/romstage";
unsigned long entry;
diff --git a/src/mainboard/hp/dl165_g6_fam10/Kconfig b/src/mainboard/hp/dl165_g6_fam10/Kconfig
index cdff24f..547cc21 100644
--- a/src/mainboard/hp/dl165_g6_fam10/Kconfig
+++ b/src/mainboard/hp/dl165_g6_fam10/Kconfig
@@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_BUS_CONFIG
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
+ select HAS_MAINBOARD_BOOTBLOCK
select LIFT_BSP_APIC_ID
select BOARD_ROMSIZE_KB_1024
select RAMINIT_SYSINFO
@@ -90,10 +91,6 @@ config HEAP_SIZE
hex
default 0xc0000
-config BOOTBLOCK_SOUTHBRIDGE_INIT
- string
- default "mainboard/hp/dl165_g6_fam10/bootblock.c"
-
config MMCONF_SUPPORT_DEFAULT
bool
default y
diff --git a/src/mainboard/hp/dl165_g6_fam10/bootblock.c b/src/mainboard/hp/dl165_g6_fam10/bootblock.c
index 2c56c4c..e7c0680 100644
--- a/src/mainboard/hp/dl165_g6_fam10/bootblock.c
+++ b/src/mainboard/hp/dl165_g6_fam10/bootblock.c
@@ -18,6 +18,9 @@ static inline void shc4307_exit_ext_func_mode(device_t dev)
#define DBG_DEV PNP_DEV(SCH4307_CONFIG_PORT, 0x3)
#define REGS_DEV PNP_DEV(SCH4307_CONFIG_PORT, 0xa)
+/* FIXME: This appears to be a super-io initialisation,
+ * placed in the mainboard directory.
+ */
void shc4307_init(void)
{
shc4307_enter_ext_func_mode(CMOS_DEV);
@@ -43,6 +46,11 @@ void shc4307_init(void)
shc4307_exit_ext_func_mode(CMOS_DEV);
}
-static void bootblock_southbridge_init(void) {
+static unsigned long init_mainboard(int bsp_cpu)
+{
+ if (!bsp_cpu) return 0;
+ init_northbridge_amd_amdfam10();
+ //init_southbridge_broadcom_bcm5785();
shc4307_init();
+ return 0;
}
diff --git a/src/northbridge/amd/agesa/family10/Kconfig b/src/northbridge/amd/agesa/family10/Kconfig
index 62a6cd4..0bb16d9 100755
--- a/src/northbridge/amd/agesa/family10/Kconfig
+++ b/src/northbridge/amd/agesa/family10/Kconfig
@@ -41,9 +41,6 @@ config MMCONF_BASE_ADDRESS
config MMCONF_BUS_NUMBER
int
default 256
-config BOOTBLOCK_NORTHBRIDGE_INIT
- string
- default "northbridge/amd/agesa/family10/bootblock.c"
endif #NORTHBRIDGE_AMD_AGESA_FAMILY10
source "src/northbridge/amd/agesa/family10/root_complex/Kconfig"
diff --git a/src/northbridge/amd/agesa/family10/bootblock.c b/src/northbridge/amd/agesa/family10/bootblock.c
deleted file mode 100644
index f6ae8be..0000000
--- a/src/northbridge/amd/agesa/family10/bootblock.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- *****************************************************************************
- *
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * ***************************************************************************
- *
- */
-
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <device/pci_def.h>
-
-static void bootblock_northbridge_init(void) {
-}
diff --git a/src/northbridge/amd/agesa/family12/Kconfig b/src/northbridge/amd/agesa/family12/Kconfig
index fc3c436..8ab5de8 100755
--- a/src/northbridge/amd/agesa/family12/Kconfig
+++ b/src/northbridge/amd/agesa/family12/Kconfig
@@ -73,7 +73,3 @@ if DIMM_DDR3
endif
endif
-config BOOTBLOCK_NORTHBRIDGE_INIT
- string
- default "northbridge/amd/agesa/family12/bootblock.c"
- depends on NORTHBRIDGE_AMD_AGESA_FAMILY12
diff --git a/src/northbridge/amd/agesa/family12/bootblock.c b/src/northbridge/amd/agesa/family12/bootblock.c
deleted file mode 100644
index f6ae8be..0000000
--- a/src/northbridge/amd/agesa/family12/bootblock.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- *****************************************************************************
- *
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * ***************************************************************************
- *
- */
-
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <device/pci_def.h>
-
-static void bootblock_northbridge_init(void) {
-}
diff --git a/src/northbridge/amd/agesa/family14/Kconfig b/src/northbridge/amd/agesa/family14/Kconfig
index 44f93c1..e462153 100644
--- a/src/northbridge/amd/agesa/family14/Kconfig
+++ b/src/northbridge/amd/agesa/family14/Kconfig
@@ -39,8 +39,4 @@ config MMCONF_BUS_NUMBER
int
default 16
-config BOOTBLOCK_NORTHBRIDGE_INIT
- string
- default "northbridge/amd/agesa/family14/bootblock.c"
-
endif
diff --git a/src/northbridge/amd/agesa/family14/bootblock.c b/src/northbridge/amd/agesa/family14/bootblock.c
deleted file mode 100644
index f6ae8be..0000000
--- a/src/northbridge/amd/agesa/family14/bootblock.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- *****************************************************************************
- *
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * ***************************************************************************
- *
- */
-
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <device/pci_def.h>
-
-static void bootblock_northbridge_init(void) {
-}
diff --git a/src/northbridge/amd/agesa/family15/Kconfig b/src/northbridge/amd/agesa/family15/Kconfig
index 52f7a1e..382c1af 100644
--- a/src/northbridge/amd/agesa/family15/Kconfig
+++ b/src/northbridge/amd/agesa/family15/Kconfig
@@ -41,9 +41,6 @@ config MMCONF_BASE_ADDRESS
config MMCONF_BUS_NUMBER
int
default 64
-config BOOTBLOCK_NORTHBRIDGE_INIT
- string
- default "northbridge/amd/agesa/family15/bootblock.c"
endif #NORTHBRIDGE_AMD_AGESA_FAMILY15
source "src/northbridge/amd/agesa/family15/root_complex/Kconfig"
diff --git a/src/northbridge/amd/agesa/family15/bootblock.c b/src/northbridge/amd/agesa/family15/bootblock.c
deleted file mode 100644
index fc62c3e..0000000
--- a/src/northbridge/amd/agesa/family15/bootblock.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <device/pci_def.h>
-
-static void bootblock_northbridge_init(void) {
-}
diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig
index a14339e..633d378 100644
--- a/src/northbridge/amd/amdfam10/Kconfig
+++ b/src/northbridge/amd/amdfam10/Kconfig
@@ -59,10 +59,6 @@ config MMCONF_BUS_NUMBER
int
default 256
-config BOOTBLOCK_NORTHBRIDGE_INIT
- string
- default "northbridge/amd/amdfam10/bootblock.c"
-
config SB_HT_CHAIN_UNITID_OFFSET_ONLY
bool
default n
diff --git a/src/northbridge/amd/amdfam10/bootblock.c b/src/northbridge/amd/amdfam10/bootblock.c
index 612004a..328e9ad 100644
--- a/src/northbridge/amd/amdfam10/bootblock.c
+++ b/src/northbridge/amd/amdfam10/bootblock.c
@@ -3,7 +3,7 @@
#include <device/pci_def.h>
#include "northbridge/amd/amdfam10/early_ht.c"
-static void bootblock_northbridge_init(void) {
+static void init_northbridge_amd_amdfam10(void) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
/* mov bsp to bus 0xff when > 8 nodes */
diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig
index 70e75e9..b94ef42 100644
--- a/src/northbridge/amd/amdk8/Kconfig
+++ b/src/northbridge/amd/amdk8/Kconfig
@@ -51,10 +51,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC
bool
default n
-config BOOTBLOCK_NORTHBRIDGE_INIT
- string
- default "northbridge/amd/amdk8/bootblock.c"
-
config SB_HT_CHAIN_UNITID_OFFSET_ONLY
bool
default n
diff --git a/src/northbridge/amd/amdk8/bootblock.c b/src/northbridge/amd/amdk8/bootblock.c
index b5395bb..8afd507 100644
--- a/src/northbridge/amd/amdk8/bootblock.c
+++ b/src/northbridge/amd/amdk8/bootblock.c
@@ -3,6 +3,6 @@
#include <device/pci_def.h>
#include "northbridge/amd/amdk8/early_ht.c"
-static void bootblock_northbridge_init(void) {
+static void init_northbridge_amd_amdk8(void) {
enumerate_ht_chain();
}
diff --git a/src/southbridge/amd/amd8111/Kconfig b/src/southbridge/amd/amd8111/Kconfig
index fd244c8..03d0f29 100644
--- a/src/southbridge/amd/amd8111/Kconfig
+++ b/src/southbridge/amd/amd8111/Kconfig
@@ -22,7 +22,3 @@ config SOUTHBRIDGE_AMD_AMD8111
select IOAPIC
select HAVE_HARD_RESET
-config BOOTBLOCK_SOUTHBRIDGE_INIT
- string
- default "southbridge/amd/amd8111/bootblock.c"
- depends on SOUTHBRIDGE_AMD_AMD8111
diff --git a/src/southbridge/amd/amd8111/bootblock.c b/src/southbridge/amd/amd8111/bootblock.c
index 3009c0b..d4660de 100644
--- a/src/southbridge/amd/amd8111/bootblock.c
+++ b/src/southbridge/amd/amd8111/bootblock.c
@@ -41,7 +41,7 @@ static void amd8111_enable_rom(void)
pci_io_write_config8(dev, 0x43, byte);
}
-static void bootblock_southbridge_init(void)
+static void init_southbridge_amd_amd8111(void)
{
amd8111_enable_rom();
}
diff --git a/src/southbridge/amd/cimx/sb700/Kconfig b/src/southbridge/amd/cimx/sb700/Kconfig
index 27338fc..ea5adf3 100644
--- a/src/southbridge/amd/cimx/sb700/Kconfig
+++ b/src/southbridge/amd/cimx/sb700/Kconfig
@@ -47,9 +47,6 @@ config ACPI_SCI_IRQ
default 0x9
help
Set SCI IRQ to 9.
-config BOOTBLOCK_SOUTHBRIDGE_INIT
- string
- default "southbridge/amd/cimx/sb700/bootblock.c"
config REDIRECT_SBCIMX_TRACE_TO_SERIAL
bool "Redirect AMD Southbridge CIMX Trace to serial console"
diff --git a/src/southbridge/amd/cimx/sb700/bootblock.c b/src/southbridge/amd/cimx/sb700/bootblock.c
index 401c039..657fbdd 100644
--- a/src/southbridge/amd/cimx/sb700/bootblock.c
+++ b/src/southbridge/amd/cimx/sb700/bootblock.c
@@ -90,7 +90,7 @@ static void sb700_enable_rom(void)
pci_io_write_config16(dev, 0x6c, word);
}
-static void bootblock_southbridge_init(void)
+static void init_southbridge_amd_cimx_sb700(void)
{
/* Setup the rom access for 2M */
sb700_enable_rom();
diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig
index 79624e0..fc15c42 100644
--- a/src/southbridge/amd/cimx/sb800/Kconfig
+++ b/src/southbridge/amd/cimx/sb800/Kconfig
@@ -24,9 +24,6 @@ config SOUTHBRIDGE_AMD_CIMX_SB800
select AMD_SB_CIMX
if SOUTHBRIDGE_AMD_CIMX_SB800
-config BOOTBLOCK_SOUTHBRIDGE_INIT
- string
- default "southbridge/amd/cimx/sb800/bootblock.c"
config ENABLE_IDE_COMBINED_MODE
bool "Enable SATA IDE combined mode"
diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c
index 0a339b0..9e00219 100644
--- a/src/southbridge/amd/cimx/sb800/bootblock.c
+++ b/src/southbridge/amd/cimx/sb800/bootblock.c
@@ -104,7 +104,7 @@ static void enable_clocks(void)
*acpi_mmio = reg32;
}
-static void bootblock_southbridge_init(void)
+static void init_southbridge_amd_cimx_sb800(void)
{
/* Setup the rom access for 2M */
enable_rom();
diff --git a/src/southbridge/amd/cimx/sb900/Kconfig b/src/southbridge/amd/cimx/sb900/Kconfig
index 253d73f..09edd1b 100755
--- a/src/southbridge/amd/cimx/sb900/Kconfig
+++ b/src/southbridge/amd/cimx/sb900/Kconfig
@@ -49,8 +49,5 @@ config ACPI_SCI_IRQ
help
Set SCI IRQ to 9.
-config BOOTBLOCK_SOUTHBRIDGE_INIT
- string
- default "southbridge/amd/cimx/sb900/bootblock.c"
endif #SOUTHBRIDGE_AMD_CIMX_SB900
diff --git a/src/southbridge/amd/cimx/sb900/bootblock.c b/src/southbridge/amd/cimx/sb900/bootblock.c
index e84743b..f3b53d0 100644
--- a/src/southbridge/amd/cimx/sb900/bootblock.c
+++ b/src/southbridge/amd/cimx/sb900/bootblock.c
@@ -90,7 +90,7 @@ static void sb900_enable_rom(void)
pci_io_write_config16(dev, 0x6c, word);
}
-static void bootblock_southbridge_init(void)
+static void init_southbridge_amd_cimx_sb900(void)
{
/* Setup the rom access for 2M */
sb900_enable_rom();
diff --git a/src/southbridge/amd/sb600/Kconfig b/src/southbridge/amd/sb600/Kconfig
index 8ec3967..d440212 100644
--- a/src/southbridge/amd/sb600/Kconfig
+++ b/src/southbridge/amd/sb600/Kconfig
@@ -24,9 +24,6 @@ config SOUTHBRIDGE_AMD_SB600
select HAVE_HARD_RESET
if SOUTHBRIDGE_AMD_SB600
-config BOOTBLOCK_SOUTHBRIDGE_INIT
- string
- default "southbridge/amd/sb600/bootblock.c"
config EHCI_BAR
hex
diff --git a/src/southbridge/amd/sb600/bootblock.c b/src/southbridge/amd/sb600/bootblock.c
index 45991ee..0184f73 100644
--- a/src/southbridge/amd/sb600/bootblock.c
+++ b/src/southbridge/amd/sb600/bootblock.c
@@ -64,7 +64,7 @@ static void sb600_enable_rom(void)
pci_io_write_config16(dev, 0x6e, 0xffff);
}
-static void bootblock_southbridge_init(void)
+static void init_southbridge_amd_sb600(void)
{
sb600_enable_rom();
}
diff --git a/src/southbridge/amd/sb700/Kconfig b/src/southbridge/amd/sb700/Kconfig
index 05f7d09..a6fc722 100644
--- a/src/southbridge/amd/sb700/Kconfig
+++ b/src/southbridge/amd/sb700/Kconfig
@@ -28,11 +28,6 @@ config SOUTHBRIDGE_AMD_SP5100
select IOAPIC
select HAVE_USBDEBUG
-config BOOTBLOCK_SOUTHBRIDGE_INIT
- string
- default "southbridge/amd/sb700/bootblock.c"
- depends on (SOUTHBRIDGE_AMD_SB700 || SOUTHBRIDGE_AMD_SP5100)
-
config SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT
bool
default n
diff --git a/src/southbridge/amd/sb700/bootblock.c b/src/southbridge/amd/sb700/bootblock.c
index 370cff9..b4bb686 100644
--- a/src/southbridge/amd/sb700/bootblock.c
+++ b/src/southbridge/amd/sb700/bootblock.c
@@ -64,7 +64,7 @@ static void sb700_enable_rom(void)
pci_io_write_config16(dev, 0x6e, 0xffff);
}
-static void bootblock_southbridge_init(void)
+static void init_southbridge_amd_sb700(void)
{
sb700_enable_rom();
}
diff --git a/src/southbridge/amd/sb800/Kconfig b/src/southbridge/amd/sb800/Kconfig
index 592f9a7..5490c56 100644
--- a/src/southbridge/amd/sb800/Kconfig
+++ b/src/southbridge/amd/sb800/Kconfig
@@ -23,11 +23,6 @@ config SOUTHBRIDGE_AMD_SB800
select HAVE_USBDEBUG
select HAVE_HARD_RESET
-config BOOTBLOCK_SOUTHBRIDGE_INIT
- string
- default "southbridge/amd/sb800/bootblock.c"
- depends on SOUTHBRIDGE_AMD_SB800
-
config SOUTHBRIDGE_AMD_SB800_SKIP_ISA_DMA_INIT
bool
default n
diff --git a/src/southbridge/amd/sb800/bootblock.c b/src/southbridge/amd/sb800/bootblock.c
index 30d6ac6..6245dca 100644
--- a/src/southbridge/amd/sb800/bootblock.c
+++ b/src/southbridge/amd/sb800/bootblock.c
@@ -62,7 +62,7 @@ static void sb800_enable_rom(void)
pci_io_write_config16(dev, 0x6e, 0xffff);
}
-static void bootblock_southbridge_init(void)
+static void init_southbridge_amd_sb800(void)
{
sb800_enable_rom();
}
diff --git a/src/southbridge/broadcom/bcm5785/Kconfig b/src/southbridge/broadcom/bcm5785/Kconfig
index d72afd8..286c19b 100644
--- a/src/southbridge/broadcom/bcm5785/Kconfig
+++ b/src/southbridge/broadcom/bcm5785/Kconfig
@@ -2,7 +2,3 @@ config SOUTHBRIDGE_BROADCOM_BCM5785
bool
select HAVE_HARD_RESET
-config BOOTBLOCK_SOUTHBRIDGE_INIT
- string
- default "southbridge/broadcom/bcm5785/bootblock.c"
- depends on SOUTHBRIDGE_BROADCOM_BCM5785
diff --git a/src/southbridge/broadcom/bcm5785/bootblock.c b/src/southbridge/broadcom/bcm5785/bootblock.c
index cadda53..e1e5f31 100644
--- a/src/southbridge/broadcom/bcm5785/bootblock.c
+++ b/src/southbridge/broadcom/bcm5785/bootblock.c
@@ -38,7 +38,7 @@ static void bcm5785_enable_rom(void)
pci_write_config8(dev, 0x41, byte);
}
-static void bootblock_southbridge_init(void)
+static void init_southbridge_broadcom_bcm5785(void)
{
bcm5785_enable_rom();
}
diff --git a/src/southbridge/intel/i82371eb/Kconfig b/src/southbridge/intel/i82371eb/Kconfig
index 7e5109a..a5c5eb8 100644
--- a/src/southbridge/intel/i82371eb/Kconfig
+++ b/src/southbridge/intel/i82371eb/Kconfig
@@ -2,8 +2,3 @@ config SOUTHBRIDGE_INTEL_I82371EB
bool
select HAVE_ACPI_RESUME if HAVE_ACPI_TABLES
-config BOOTBLOCK_SOUTHBRIDGE_INIT
- string
- default "southbridge/intel/i82371eb/bootblock.c"
- depends on SOUTHBRIDGE_INTEL_I82371EB
-
diff --git a/src/southbridge/intel/i82371eb/bootblock.c b/src/southbridge/intel/i82371eb/bootblock.c
index 07fa0bc..a875723 100644
--- a/src/southbridge/intel/i82371eb/bootblock.c
+++ b/src/southbridge/intel/i82371eb/bootblock.c
@@ -48,7 +48,7 @@ static void i82371eb_enable_rom(void)
pci_write_config16(dev, XBCS, reg16);
}
-static void bootblock_southbridge_init(void)
+static void init_southbridge_intel_i82371eb(void)
{
i82371eb_enable_rom();
}
diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig
index 3550954..a50e0b1 100644
--- a/src/southbridge/intel/i82801gx/Kconfig
+++ b/src/southbridge/intel/i82801gx/Kconfig
@@ -38,10 +38,5 @@ config USBDEBUG_DEFAULT_PORT
int
default 1
-config BOOTBLOCK_SOUTHBRIDGE_INIT
- string
- default "southbridge/intel/i82801gx/bootblock.c"
- depends on SOUTHBRIDGE_INTEL_I82801GX
-
endif
diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c
index 39b0bd4..a0f73b3 100644
--- a/src/southbridge/intel/i82801gx/bootblock.c
+++ b/src/southbridge/intel/i82801gx/bootblock.c
@@ -33,7 +33,7 @@ static void enable_spi_prefetch(void)
pci_write_config8(dev, 0xdc, reg8);
}
-static void bootblock_southbridge_init(void)
+static void init_southbridge_intel_i82801gx(void)
{
enable_spi_prefetch();
}
diff --git a/src/southbridge/nvidia/ck804/Kconfig b/src/southbridge/nvidia/ck804/Kconfig
index 97927d7..01cff02 100644
--- a/src/southbridge/nvidia/ck804/Kconfig
+++ b/src/southbridge/nvidia/ck804/Kconfig
@@ -6,9 +6,9 @@ config SOUTHBRIDGE_NVIDIA_CK804
if SOUTHBRIDGE_NVIDIA_CK804
-config BOOTBLOCK_SOUTHBRIDGE_INIT
- string
- default "southbridge/nvidia/ck804/bootblock.c"
+config ID_SECTION_OFFSET
+ hex
+ default 0x80
config EHCI_BAR
hex
diff --git a/src/southbridge/nvidia/ck804/bootblock.c b/src/southbridge/nvidia/ck804/bootblock.c
index 29c10c8..3175606 100644
--- a/src/southbridge/nvidia/ck804/bootblock.c
+++ b/src/southbridge/nvidia/ck804/bootblock.c
@@ -42,7 +42,7 @@ static void ck804_enable_rom(void)
pci_write_config8(addr, 0x88, byte);
}
-static void bootblock_southbridge_init(void)
+static void init_southbridge_nvidia_ck804(void)
{
ck804_enable_rom();
}
diff --git a/src/southbridge/nvidia/mcp55/Kconfig b/src/southbridge/nvidia/mcp55/Kconfig
index cd6009d..e1bb06d 100644
--- a/src/southbridge/nvidia/mcp55/Kconfig
+++ b/src/southbridge/nvidia/mcp55/Kconfig
@@ -6,9 +6,9 @@ config SOUTHBRIDGE_NVIDIA_MCP55
if SOUTHBRIDGE_NVIDIA_MCP55
-config BOOTBLOCK_SOUTHBRIDGE_INIT
- string
- default "southbridge/nvidia/mcp55/bootblock.c"
+config ID_SECTION_OFFSET
+ hex
+ default 0x80
config EHCI_BAR
hex
diff --git a/src/southbridge/nvidia/mcp55/bootblock.c b/src/southbridge/nvidia/mcp55/bootblock.c
index affb025..6fb6dbb 100644
--- a/src/southbridge/nvidia/mcp55/bootblock.c
+++ b/src/southbridge/nvidia/mcp55/bootblock.c
@@ -53,7 +53,7 @@ static void mcp55_enable_rom(void)
pci_write_config16(addr, 0x90, word);
}
-static void bootblock_southbridge_init(void)
+static void init_southbridge_nvidia_mcp55(void)
{
mcp55_enable_rom();
}
diff --git a/src/southbridge/sis/sis966/Kconfig b/src/southbridge/sis/sis966/Kconfig
index 03dd6b1..ae9a139 100644
--- a/src/southbridge/sis/sis966/Kconfig
+++ b/src/southbridge/sis/sis966/Kconfig
@@ -4,9 +4,9 @@ config SOUTHBRIDGE_SIS_SIS966
select HAVE_USBDEBUG
select HAVE_HARD_RESET
-config BOOTBLOCK_SOUTHBRIDGE_INIT
- string
- default "southbridge/sis/sis966/bootblock.c" if SOUTHBRIDGE_SIS_SIS966
+config ID_SECTION_OFFSET
+ hex
+ default 0x80 if SOUTHBRIDGE_SIS_SIS966
config EHCI_BAR
hex
@@ -15,3 +15,4 @@ config EHCI_BAR
config EHCI_DEBUG_OFFSET
hex
default 0x98 if SOUTHBRIDGE_SIS_SIS966
+
diff --git a/src/southbridge/sis/sis966/bootblock.c b/src/southbridge/sis/sis966/bootblock.c
index 1ff3cda..45ab81b 100644
--- a/src/southbridge/sis/sis966/bootblock.c
+++ b/src/southbridge/sis/sis966/bootblock.c
@@ -41,7 +41,7 @@ static void sis966_enable_rom(void)
pci_write_config8(addr, 0x40, pci_read_config8(addr, 0x40) | 0x11);
}
-static void bootblock_southbridge_init(void)
+static void init_southbridge_sis_sis966(void)
{
sis966_enable_rom();
}
diff --git a/src/southbridge/via/vt8237r/Kconfig b/src/southbridge/via/vt8237r/Kconfig
index d0a6deb..9aa1b97 100644
--- a/src/southbridge/via/vt8237r/Kconfig
+++ b/src/southbridge/via/vt8237r/Kconfig
@@ -27,7 +27,3 @@ config EPIA_VT8237R_INIT
default n
depends on SOUTHBRIDGE_VIA_VT8237R
-config BOOTBLOCK_SOUTHBRIDGE_INIT
- string
- default "southbridge/via/vt8237r/bootblock.c"
- depends on SOUTHBRIDGE_VIA_VT8237R
diff --git a/src/southbridge/via/vt8237r/bootblock.c b/src/southbridge/via/vt8237r/bootblock.c
index 8df37aa..0ca0533 100644
--- a/src/southbridge/via/vt8237r/bootblock.c
+++ b/src/southbridge/via/vt8237r/bootblock.c
@@ -21,7 +21,7 @@
#include <arch/romcc_io.h>
#include <device/pci_ids.h>
-static void bootblock_southbridge_init(void)
+static void init_southbridge_via_vt8237r(void)
{
device_t dev;
/* don't walk other busses, HT is not enabled */
More information about the coreboot
mailing list