[coreboot] New patch to review for coreboot: 69dcef7 Intel model_6ex: minor CAR fixes
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Thu Feb 16 22:54:33 CET 2012
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/643
-gerrit
commit 69dcef76380deb90f2dca58a086393c00b15e6c3
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Thu Feb 16 22:38:16 2012 +0200
Intel model_6ex: minor CAR fixes
Change-Id: Ibb93e889b3a0af87b89345c462e331881e78686a
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/cpu/intel/model_6ex/cache_as_ram.inc | 23 +++++++++++++----------
1 files changed, 13 insertions(+), 10 deletions(-)
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index cbfa4f8..5a29744 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -21,6 +21,10 @@
#include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/post_code.h>
+#include <cpu/x86/lapic_def.h>
+
+/* Macro to access Local APIC registers at default base. */
+#define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x)
#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_MAXPHYADDR - 32) - 1)
@@ -37,9 +41,9 @@ cache_as_ram:
post_code(0x20)
/* Send INIT IPI to all excluding ourself. */
- movl $0x000C4500, %eax
- movl $0xFEE00300, %esi
- movl %eax, (%esi)
+ movl LAPIC(ICR), %edi
+ movl $(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT), %eax
+ movl %eax, (%edi)
/* Zero out all fixed range and variable range MTRRs. */
movl $mtrr_table, %esi
@@ -91,11 +95,10 @@ clear_mtrrs:
movl %eax, %cr0
/* Clear the cache memory reagion. */
- movl $CACHE_AS_RAM_BASE, %esi
- movl %esi, %edi
- movl $(CACHE_AS_RAM_SIZE / 4), %ecx
- // movl $0x23322332, %eax
+ cld
xorl %eax, %eax
+ movl $CACHE_AS_RAM_BASE, %edi
+ movl $(CACHE_AS_RAM_SIZE / 4), %ecx
rep stosl
/* Enable Cache-as-RAM mode by disabling cache. */
@@ -130,11 +133,10 @@ clear_mtrrs:
/* Set up the stack pointer. */
#if CONFIG_USBDEBUG
/* Leave some space for the struct ehci_debug_info. */
- movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax
+ movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %esp
#else
- movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax
+ movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %esp
#endif
- movl %eax, %esp
/* Restore the BIST result. */
movl %ebp, %eax
@@ -145,6 +147,7 @@ clear_mtrrs:
/* Call romstage.c main function. */
call main
+ addl $4, %esp
post_code(0x2f)
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