[coreboot] New patch to review for coreboot: 213eb80 Force SB800 bootblock to use I/O for PCI config
Marc Jones (marcj303@gmail.com)
gerrit at coreboot.org
Tue Feb 14 01:11:21 CET 2012
Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/630
-gerrit
commit 213eb80a8a071403ca9448dc08b8e00b95f31e67
Author: Dave Frodin <dave.frodin at se-eng.com>
Date: Thu Feb 2 14:56:23 2012 -0700
Force SB800 bootblock to use I/O for PCI config
If PCI config cycles use MMIO instead of I/O in the bootblock
code the cycles will go nowhere since the MMIO feature hasn't been
configured yet. This change forces the cycles to use I/O.
Change-Id: I93dec45f7cd6764cef7736c774a4d4e61bf7d7e0
Signed-off-by: Marc Jones <marcj303 at gmail.com>
---
src/southbridge/amd/sb800/bootblock.c | 12 ++++++------
1 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/southbridge/amd/sb800/bootblock.c b/src/southbridge/amd/sb800/bootblock.c
index 18eae24..30d6ac6 100644
--- a/src/southbridge/amd/sb800/bootblock.c
+++ b/src/southbridge/amd/sb800/bootblock.c
@@ -39,15 +39,15 @@ static void sb800_enable_rom(void)
dev = PCI_DEV(0, 0x14, 3);
/* Decode variable LPC ROM address ranges 1 and 2. */
- reg8 = pci_read_config8(dev, 0x48);
+ reg8 = pci_io_read_config8(dev, 0x48);
reg8 |= (1 << 3) | (1 << 4);
- pci_write_config8(dev, 0x48, reg8);
+ pci_io_write_config8(dev, 0x48, reg8);
/* LPC ROM address range 1: */
/* Enable LPC ROM range mirroring start at 0x000e(0000). */
- pci_write_config16(dev, 0x68, 0x000e);
+ pci_io_write_config16(dev, 0x68, 0x000e);
/* Enable LPC ROM range mirroring end at 0x000f(ffff). */
- pci_write_config16(dev, 0x6a, 0x000f);
+ pci_io_write_config16(dev, 0x6a, 0x000f);
/* LPC ROM address range 2: */
/*
@@ -57,9 +57,9 @@ static void sb800_enable_rom(void)
* 0xffe0(0000): 2MB
* 0xffc0(0000): 4MB
*/
- pci_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6));
+ pci_io_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6));
/* Enable LPC ROM range end at 0xffff(ffff). */
- pci_write_config16(dev, 0x6e, 0xffff);
+ pci_io_write_config16(dev, 0x6e, 0xffff);
}
static void bootblock_southbridge_init(void)
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