[coreboot] New patch to review for coreboot: b23d0dc Intel cpus: Include CAR from socket

Kyösti Mälkki (kyosti.malkki@gmail.com) gerrit at coreboot.org
Mon Feb 13 21:15:22 CET 2012


Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/626

-gerrit

commit b23d0dc51cc42e08152e63753ed7e87455f8dd16
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Mon Feb 13 13:38:27 2012 +0200

    Intel cpus: Include CAR from socket
    
    It was not obvious which CAR was compiled in. Also build would fail
    if a socket included two models with both having an include for CAR.
    
    Change-Id: I000c2e24807c3d99347a43d120333c13fbf91af4
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/cpu/intel/model_6ex/Makefile.inc        |    1 -
 src/cpu/intel/socket_LGA771/Makefile.inc    |    1 +
 src/cpu/intel/socket_mFCPGA478/Makefile.inc |    1 +
 3 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/src/cpu/intel/model_6ex/Makefile.inc b/src/cpu/intel/model_6ex/Makefile.inc
index 0053ae7..cc4dc7b 100644
--- a/src/cpu/intel/model_6ex/Makefile.inc
+++ b/src/cpu/intel/model_6ex/Makefile.inc
@@ -1,4 +1,3 @@
 driver-y += model_6ex_init.c
 subdirs-y += ../../x86/name
 
-cpu_incs += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
diff --git a/src/cpu/intel/socket_LGA771/Makefile.inc b/src/cpu/intel/socket_LGA771/Makefile.inc
index 319430f..ef520a3 100644
--- a/src/cpu/intel/socket_LGA771/Makefile.inc
+++ b/src/cpu/intel/socket_LGA771/Makefile.inc
@@ -9,3 +9,4 @@ subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 subdirs-y += ../hyperthreading
 
+cpu_incs += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
diff --git a/src/cpu/intel/socket_mFCPGA478/Makefile.inc b/src/cpu/intel/socket_mFCPGA478/Makefile.inc
index 74433a2..29973af 100644
--- a/src/cpu/intel/socket_mFCPGA478/Makefile.inc
+++ b/src/cpu/intel/socket_mFCPGA478/Makefile.inc
@@ -12,3 +12,4 @@ subdirs-y += ../microcode
 subdirs-y += ../hyperthreading
 subdirs-y += ../speedstep
 
+cpu_incs += $(src)/cpu/intel/model_6ex/cache_as_ram.inc




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