[coreboot] New patch to review for coreboot: ede2da9 VIA cpus: apply un-written naming rules

Kyösti Mälkki (kyosti.malkki@gmail.com) gerrit at coreboot.org
Thu Feb 9 15:54:08 CET 2012


Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/614

-gerrit

commit ede2da9d2d9fffcf8a57d19958bedf595cc46f01
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Thu Feb 9 16:51:38 2012 +0200

    VIA cpus: apply un-written naming rules
    
    Rename files and directories:
      model_c3 -> c3
      model_c7 -> c7
    
    Change-Id: If144fc501e8ae44b347ac44fa90c689c33a8e126
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/cpu/via/Kconfig                         |    4 +-
 src/cpu/via/Makefile.inc                    |    4 +-
 src/cpu/via/c3/Kconfig                      |   11 ++
 src/cpu/via/c3/Makefile.inc                 |    8 +
 src/cpu/via/c3/c3_init.c                    |   53 ++++++
 src/cpu/via/c7/Kconfig                      |   21 +++
 src/cpu/via/c7/Makefile.inc                 |   10 ++
 src/cpu/via/c7/c7_init.c                    |  231 +++++++++++++++++++++++++++
 src/cpu/via/model_c3/Kconfig                |    4 -
 src/cpu/via/model_c3/Makefile.inc           |    8 -
 src/cpu/via/model_c3/model_c3_init.c        |   53 ------
 src/cpu/via/model_c7/Kconfig                |   23 ---
 src/cpu/via/model_c7/Makefile.inc           |   10 --
 src/cpu/via/model_c7/model_c7_init.c        |  231 ---------------------------
 src/mainboard/bcom/winnetp680/devicetree.cb |    2 +-
 src/mainboard/jetway/j7f24/devicetree.cb    |    2 +-
 src/mainboard/via/epia-cn/devicetree.cb     |    2 +-
 src/mainboard/via/epia-m/devicetree.cb      |    2 +-
 src/mainboard/via/epia-m700/devicetree.cb   |    2 +-
 src/mainboard/via/epia-n/devicetree.cb      |    2 +-
 src/mainboard/via/epia/devicetree.cb        |    2 +-
 src/mainboard/via/pc2500e/devicetree.cb     |    2 +-
 src/mainboard/via/vt8454c/devicetree.cb     |    2 +-
 23 files changed, 347 insertions(+), 342 deletions(-)

diff --git a/src/cpu/via/Kconfig b/src/cpu/via/Kconfig
index 006fb8b..570d408 100644
--- a/src/cpu/via/Kconfig
+++ b/src/cpu/via/Kconfig
@@ -1,2 +1,2 @@
-source src/cpu/via/model_c3/Kconfig
-source src/cpu/via/model_c7/Kconfig
+source src/cpu/via/c3/Kconfig
+source src/cpu/via/c7/Kconfig
diff --git a/src/cpu/via/Makefile.inc b/src/cpu/via/Makefile.inc
index 512f82b..2616111 100644
--- a/src/cpu/via/Makefile.inc
+++ b/src/cpu/via/Makefile.inc
@@ -1,3 +1,3 @@
-subdirs-$(CONFIG_CPU_VIA_C7) += model_c7
-subdirs-$(CONFIG_CPU_VIA_C3) += model_c3
+subdirs-$(CONFIG_CPU_VIA_C7) += c7
+subdirs-$(CONFIG_CPU_VIA_C3) += c3
 
diff --git a/src/cpu/via/c3/Kconfig b/src/cpu/via/c3/Kconfig
new file mode 100644
index 0000000..a5b4f22
--- /dev/null
+++ b/src/cpu/via/c3/Kconfig
@@ -0,0 +1,11 @@
+config CPU_VIA_C3
+	bool
+
+if CPU_VIA_C3
+
+config CPU_SPECIFIC_OPTIONS
+	def_bool y
+	select UDELAY_TSC
+	select MMX
+
+endif # CPU_VIA_C3
diff --git a/src/cpu/via/c3/Makefile.inc b/src/cpu/via/c3/Makefile.inc
new file mode 100644
index 0000000..e6b889a
--- /dev/null
+++ b/src/cpu/via/c3/Makefile.inc
@@ -0,0 +1,8 @@
+subdirs-y += ../../x86/tsc
+subdirs-y += ../../x86/mtrr
+subdirs-y += ../../x86/lapic
+subdirs-y += ../../x86/cache
+subdirs-y += ../../x86/smm
+subdirs-y += ../../intel/microcode
+
+driver-y += c3_init.c
diff --git a/src/cpu/via/c3/c3_init.c b/src/cpu/via/c3/c3_init.c
new file mode 100644
index 0000000..7d94384
--- /dev/null
+++ b/src/cpu/via/c3/c3_init.c
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/x86/cache.h>
+
+static void c3_init(device_t dev)
+{
+	x86_enable_cache();
+	x86_setup_mtrrs();
+	x86_mtrr_check();
+
+	/* Enable the local cpu apics */
+	setup_lapic();
+};
+
+static struct device_operations cpu_dev_ops = {
+	.init     = c3_init,
+};
+
+static struct cpu_device_id cpu_table[] = {
+	{ X86_VENDOR_CENTAUR, 0x0670 },		// VIA C3 Samual 2 + Ezra
+	{ X86_VENDOR_CENTAUR, 0x0680 },		// VIA C3 Ezra-T
+	{ X86_VENDOR_CENTAUR, 0x0690 },		// VIA C3 Nehemiah
+	{ 0, 0 },
+};
+
+static const struct cpu_driver driver __cpu_driver = {
+	.ops      = &cpu_dev_ops,
+	.id_table = cpu_table,
+};
diff --git a/src/cpu/via/c7/Kconfig b/src/cpu/via/c7/Kconfig
new file mode 100644
index 0000000..ebbb8f9
--- /dev/null
+++ b/src/cpu/via/c7/Kconfig
@@ -0,0 +1,21 @@
+config CPU_VIA_C7
+	bool
+
+if CPU_VIA_C7
+
+config CPU_SPECIFIC_OPTIONS
+	def_bool y
+	select UDELAY_TSC
+	select MMX
+	select SSE2
+	select CACHE_AS_RAM
+
+config DCACHE_RAM_BASE
+	hex
+	default 0xffef0000
+
+config DCACHE_RAM_SIZE
+	hex
+	default 0x8000
+
+endif # CPU_VIA_C7
diff --git a/src/cpu/via/c7/Makefile.inc b/src/cpu/via/c7/Makefile.inc
new file mode 100644
index 0000000..5300f5d
--- /dev/null
+++ b/src/cpu/via/c7/Makefile.inc
@@ -0,0 +1,10 @@
+subdirs-y += ../../x86/tsc
+subdirs-y += ../../x86/mtrr
+subdirs-y += ../../x86/lapic
+subdirs-y += ../../x86/cache
+subdirs-y += ../../x86/smm
+subdirs-y += ../../intel/microcode
+
+driver-y += c7_init.c
+
+cpu_incs += $(src)/cpu/via/car/cache_as_ram.inc
diff --git a/src/cpu/via/c7/c7_init.c b/src/cpu/via/c7/c7_init.c
new file mode 100644
index 0000000..510e66d
--- /dev/null
+++ b/src/cpu/via/c7/c7_init.c
@@ -0,0 +1,231 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <console/console.h>
+#include <delay.h>
+#include <stdlib.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/x86/cache.h>
+
+#define MSR_IA32_PERF_STATUS	0x00000198
+#define MSR_IA32_PERF_CTL	0x00000199
+#define MSR_IA32_MISC_ENABLE	0x000001a0
+
+static int c7a_speed_translation[] = {
+//      LFM     HFM
+	0x0409, 0x0f13,		// 400MHz, 844mV --> 1500MHz, 1.004V    C7-M
+	0x0409, 0x1018,		// 400MHz, 844mV --> 1600MHz, 1.084V
+	0x0409, 0x0c18,		// 533MHz, 844mV --> 1600MHz, 1.084V
+	0x0409, 0x121c,		// 400MHz, 844mV --> 1800MHz, 1.148V
+	0x0409, 0x0e1c,		// 533MHz, 844mV --> 1860MHz, 1.148V
+	0x0409, 0x141f,		// 400MHz, 844mV --> 2000MHz, 1.196V
+	0x0409, 0x0f1f,		// 533MHz, 844mV --> 2000MHz, 1.196V
+	0x0406, 0x0a06,		// 400MHz, 796mV --> 1000MHz, 796mV     C7-M ULV
+	0x0406, 0x0a09,		// 400MHz, 796mV --> 1000MHz, 844mV
+	0x0406, 0x0c09,		// 400MHz, 796mV --> 1200MHz, 844mV
+	0x0406, 0x0f10,		// 400MHz, 796mV --> 1500MHz, 956mV
+};
+
+static int c7d_speed_translation[] = {
+//      LFM     HFM
+	0x0409, 0x1018,		// 400MHz, 844mV --> 1600MHz, 1.084V    C7-M
+	0x0409, 0x121f,		// 400MHz, 844mV --> 1800MHz, 1.196V
+	0x0809, 0x121f,		// 800MHz, 844mV --> 1800MHz, 1.196V
+	0x0409, 0x141f,		// 400MHz, 844mV --> 2000MHz, 1.196V
+	0x0809, 0x141f,		// 800MHz, 844mV --> 2000MHz, 1.196V
+	0x0406, 0x0806,		// 400MHz, 796mV --> 800MHz, 796mV      C7-M ULV
+	0x0406, 0x0a06,		// 400MHz, 796mV --> 1000MHz, 796mV
+	0x0406, 0x0c09,		// 400MHz, 796mV --> 1200MHz, 844mV
+	0x0806, 0x0c09,		// 800MHz, 796mV --> 1200MHz, 844mV
+	0x0406, 0x0f10,		// 400MHz, 796mV --> 1500MHz, 956mV
+	0x0806, 0x1010,		// 800MHz, 796mV --> 1600MHz, 956mV
+};
+
+static void set_c7_speed(int model) {
+	int cnt, current, new, i;
+	msr_t msr;
+	printk(BIOS_DEBUG, "Enabling improved C7 clock and voltage.\n");
+
+	// Enable Speedstep
+	msr = rdmsr(MSR_IA32_MISC_ENABLE);
+	msr.lo |= (1 << 16);
+	wrmsr(MSR_IA32_MISC_ENABLE, msr);
+
+	msr = rdmsr(MSR_IA32_PERF_STATUS);
+
+	printk(BIOS_INFO, "Voltage: %dmV (min %dmV; max %dmV)\n",
+		    ((int)(msr.lo & 0xff) * 16 + 700),
+		    ((int)((msr.hi >> 16) & 0xff) * 16 + 700),
+		    ((int)(msr.hi & 0xff) * 16 + 700));
+
+	printk(BIOS_INFO, "CPU multiplier: %dx (min %dx; max %dx)\n",
+		    (int)((msr.lo >> 8) & 0xff),
+		    (int)((msr.hi >> 24) & 0xff), (int)((msr.hi >> 8) & 0xff));
+
+	printk(BIOS_DEBUG, " msr.lo = %x\n", msr.lo);
+
+	/* Wait while CPU is busy */
+	cnt = 0;
+	while (msr.lo & ((1 << 16) | (1 << 17))) {
+		udelay(16);
+		msr = rdmsr(MSR_IA32_PERF_STATUS);
+		cnt++;
+		if (cnt > 128) {
+			printk(BIOS_WARNING, "Could not update multiplier and voltage.\n");
+			return;
+		}
+	}
+
+	current = msr.lo & 0xffff;
+
+	// Start out with no change.
+	new = current;
+	switch (model) {
+	case 10:		// model A
+		for (i = 0; i < ARRAY_SIZE(c7a_speed_translation); i += 2) {
+			if ((c7a_speed_translation[i] == current) &&
+			    ((c7a_speed_translation[i + 1] & 0xff00) ==
+			     (msr.hi & 0xff00))) {
+				new = c7a_speed_translation[i + 1];
+			}
+		}
+		break;
+	case 13:		// model D
+		for (i = 0; i < ARRAY_SIZE(c7d_speed_translation); i += 2) {
+			if ((c7d_speed_translation[i] == current) &&
+			    ((c7d_speed_translation[i + 1] & 0xff00) ==
+			     (msr.hi & 0xff00))) {
+				new = c7d_speed_translation[i + 1];
+			}
+		}
+		break;
+	default:
+		print_info("CPU type not known, multiplier unchanged.\n");
+	}
+
+	msr.lo = new;
+	msr.hi = 0;
+	printk(BIOS_DEBUG, " new msr.lo = %x\n", msr.lo);
+
+	wrmsr(MSR_IA32_PERF_CTL, msr);
+
+	/* Wait until the power transition ends */
+	cnt = 0;
+	do {
+		udelay(16);
+		msr = rdmsr(MSR_IA32_PERF_STATUS);
+		cnt++;
+		if (cnt > 128) {
+			printk(BIOS_WARNING, "Error while updating multiplier and voltage\n");
+			break;
+		}
+	} while (msr.lo & ((1 << 16) | (1 << 17)));
+
+	printk(BIOS_INFO, "Current voltage: %dmV\n", ((int)(msr.lo & 0xff) * 16 + 700));
+	printk(BIOS_INFO, "Current CPU multiplier: %dx\n", (int)((msr.lo >> 8) & 0xff));
+}
+
+static void c7_init(device_t dev)
+{
+	u8 brand;
+	struct cpuinfo_x86 c;
+	msr_t msr;
+
+	get_fms(&c, dev->device);
+
+	printk(BIOS_INFO, "Detected VIA ");
+
+	switch (c.x86_model) {
+	case 10:
+		msr = rdmsr(0x1153);
+		brand = (((msr.lo >> 2) ^ msr.lo) >> 18) & 3;
+		printk(BIOS_INFO, "Model A ");
+		break;
+	case 13:
+		msr = rdmsr(0x1154);
+		brand = (((msr.lo >> 4) ^ (msr.lo >> 2))) & 0x000000ff;
+		printk(BIOS_INFO, "Model D ");
+		break;
+	default:
+		printk(BIOS_INFO, "Model Unknown ");
+		brand = 0xff;
+	}
+
+	switch (brand) {
+	case 0:
+		printk(BIOS_INFO, "C7-M\n");
+		break;
+	case 1:
+		printk(BIOS_INFO, "C7\n");
+		break;
+	case 2:
+		printk(BIOS_INFO, "Eden\n");
+		break;
+	case 3:
+		printk(BIOS_INFO, "C7-D\n");
+		break;
+	default:
+		printk(BIOS_INFO, "%02x (please report)\n", brand);
+	}
+
+	/* Gear up */
+	set_c7_speed(c.x86_model);
+
+	/* Enable APIC */
+	msr = rdmsr(0x1107);
+	msr.lo |= 1<<24;
+	wrmsr(0x1107, msr);
+
+	/* Turn on cache */
+	x86_enable_cache();
+
+	/* Set up Memory Type Range Registers */
+	x86_setup_mtrrs();
+	x86_mtrr_check();
+
+	/* Enable the local cpu apics */
+	setup_lapic();
+};
+
+static struct device_operations cpu_dev_ops = {
+	.init = c7_init,
+};
+
+/* Look in arch/x86/lib/cpu.c:cpu_initialize. If there is no CPU with an exact
+ * ID, the cpu mask (stepping) is masked out and the check is repeated. This
+ * allows us to keep the table significantly smaller.
+ */
+
+static struct cpu_device_id cpu_table[] = {
+	{X86_VENDOR_CENTAUR, 0x06A0},	// VIA C7 Esther
+	{X86_VENDOR_CENTAUR, 0x06A9},	// VIA C7 Esther
+	{X86_VENDOR_CENTAUR, 0x06D0},	// VIA C7-M
+	{0, 0},
+};
+
+static const struct cpu_driver driver __cpu_driver = {
+	.ops = &cpu_dev_ops,
+	.id_table = cpu_table,
+};
diff --git a/src/cpu/via/model_c3/Kconfig b/src/cpu/via/model_c3/Kconfig
deleted file mode 100644
index d613909..0000000
--- a/src/cpu/via/model_c3/Kconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-config CPU_VIA_C3
-	bool
-	select UDELAY_TSC
-	select MMX
diff --git a/src/cpu/via/model_c3/Makefile.inc b/src/cpu/via/model_c3/Makefile.inc
deleted file mode 100644
index 320b649..0000000
--- a/src/cpu/via/model_c3/Makefile.inc
+++ /dev/null
@@ -1,8 +0,0 @@
-subdirs-y += ../../x86/tsc
-subdirs-y += ../../x86/mtrr
-subdirs-y += ../../x86/lapic
-subdirs-y += ../../x86/cache
-subdirs-y += ../../x86/smm
-subdirs-y += ../../intel/microcode
-
-driver-y += model_c3_init.c
diff --git a/src/cpu/via/model_c3/model_c3_init.c b/src/cpu/via/model_c3/model_c3_init.c
deleted file mode 100644
index 0c5315b..0000000
--- a/src/cpu/via/model_c3/model_c3_init.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * (C) 2007-2008 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <device/device.h>
-#include <cpu/cpu.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/lapic.h>
-#include <cpu/x86/cache.h>
-
-static void model_c3_init(device_t dev)
-{
-	x86_enable_cache();
-	x86_setup_mtrrs();
-	x86_mtrr_check();
-
-	/* Enable the local cpu apics */
-	setup_lapic();
-};
-
-static struct device_operations cpu_dev_ops = {
-	.init     = model_c3_init,
-};
-
-static struct cpu_device_id cpu_table[] = {
-	{ X86_VENDOR_CENTAUR, 0x0670 },		// VIA C3 Samual 2 + Ezra
-	{ X86_VENDOR_CENTAUR, 0x0680 },		// VIA C3 Ezra-T
-	{ X86_VENDOR_CENTAUR, 0x0690 },		// VIA C3 Nehemiah
-	{ 0, 0 },
-};
-
-static const struct cpu_driver driver __cpu_driver = {
-	.ops      = &cpu_dev_ops,
-	.id_table = cpu_table,
-};
diff --git a/src/cpu/via/model_c7/Kconfig b/src/cpu/via/model_c7/Kconfig
deleted file mode 100644
index 8e6f0e8..0000000
--- a/src/cpu/via/model_c7/Kconfig
+++ /dev/null
@@ -1,23 +0,0 @@
-config CPU_VIA_C7
-	bool
-
-if CPU_VIA_C7
-
-config CPU_SPECFIC_OPTIONS
-	def_bool y
-	select UDELAY_TSC
-	select MMX
-	select SSE2
-	select CACHE_AS_RAM
-
-config DCACHE_RAM_BASE
-	hex
-	default 0xffef0000
-	depends on CPU_VIA_C7
-
-config DCACHE_RAM_SIZE
-	hex
-	default 0x8000
-	depends on CPU_VIA_C7
-
-endif # CPU_VIA_C7
diff --git a/src/cpu/via/model_c7/Makefile.inc b/src/cpu/via/model_c7/Makefile.inc
deleted file mode 100644
index c6ab45e..0000000
--- a/src/cpu/via/model_c7/Makefile.inc
+++ /dev/null
@@ -1,10 +0,0 @@
-subdirs-y += ../../x86/tsc
-subdirs-y += ../../x86/mtrr
-subdirs-y += ../../x86/lapic
-subdirs-y += ../../x86/cache
-subdirs-y += ../../x86/smm
-subdirs-y += ../../intel/microcode
-
-driver-y += model_c7_init.c
-
-cpu_incs += $(src)/cpu/via/car/cache_as_ram.inc
diff --git a/src/cpu/via/model_c7/model_c7_init.c b/src/cpu/via/model_c7/model_c7_init.c
deleted file mode 100644
index 585f749..0000000
--- a/src/cpu/via/model_c7/model_c7_init.c
+++ /dev/null
@@ -1,231 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <device/device.h>
-#include <console/console.h>
-#include <delay.h>
-#include <stdlib.h>
-#include <cpu/cpu.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/lapic.h>
-#include <cpu/x86/cache.h>
-
-#define MSR_IA32_PERF_STATUS	0x00000198
-#define MSR_IA32_PERF_CTL	0x00000199
-#define MSR_IA32_MISC_ENABLE	0x000001a0
-
-static int c7a_speed_translation[] = {
-//      LFM     HFM
-	0x0409, 0x0f13,		// 400MHz, 844mV --> 1500MHz, 1.004V    C7-M
-	0x0409, 0x1018,		// 400MHz, 844mV --> 1600MHz, 1.084V
-	0x0409, 0x0c18,		// 533MHz, 844mV --> 1600MHz, 1.084V
-	0x0409, 0x121c,		// 400MHz, 844mV --> 1800MHz, 1.148V
-	0x0409, 0x0e1c,		// 533MHz, 844mV --> 1860MHz, 1.148V
-	0x0409, 0x141f,		// 400MHz, 844mV --> 2000MHz, 1.196V
-	0x0409, 0x0f1f,		// 533MHz, 844mV --> 2000MHz, 1.196V
-	0x0406, 0x0a06,		// 400MHz, 796mV --> 1000MHz, 796mV     C7-M ULV
-	0x0406, 0x0a09,		// 400MHz, 796mV --> 1000MHz, 844mV
-	0x0406, 0x0c09,		// 400MHz, 796mV --> 1200MHz, 844mV
-	0x0406, 0x0f10,		// 400MHz, 796mV --> 1500MHz, 956mV
-};
-
-static int c7d_speed_translation[] = {
-//      LFM     HFM
-	0x0409, 0x1018,		// 400MHz, 844mV --> 1600MHz, 1.084V    C7-M
-	0x0409, 0x121f,		// 400MHz, 844mV --> 1800MHz, 1.196V
-	0x0809, 0x121f,		// 800MHz, 844mV --> 1800MHz, 1.196V
-	0x0409, 0x141f,		// 400MHz, 844mV --> 2000MHz, 1.196V
-	0x0809, 0x141f,		// 800MHz, 844mV --> 2000MHz, 1.196V
-	0x0406, 0x0806,		// 400MHz, 796mV --> 800MHz, 796mV      C7-M ULV
-	0x0406, 0x0a06,		// 400MHz, 796mV --> 1000MHz, 796mV
-	0x0406, 0x0c09,		// 400MHz, 796mV --> 1200MHz, 844mV
-	0x0806, 0x0c09,		// 800MHz, 796mV --> 1200MHz, 844mV
-	0x0406, 0x0f10,		// 400MHz, 796mV --> 1500MHz, 956mV
-	0x0806, 0x1010,		// 800MHz, 796mV --> 1600MHz, 956mV
-};
-
-static void set_c7_speed(int model) {
-	int cnt, current, new, i;
-	msr_t msr;
-	printk(BIOS_DEBUG, "Enabling improved C7 clock and voltage.\n");
-
-	// Enable Speedstep
-	msr = rdmsr(MSR_IA32_MISC_ENABLE);
-	msr.lo |= (1 << 16);
-	wrmsr(MSR_IA32_MISC_ENABLE, msr);
-
-	msr = rdmsr(MSR_IA32_PERF_STATUS);
-
-	printk(BIOS_INFO, "Voltage: %dmV (min %dmV; max %dmV)\n",
-		    ((int)(msr.lo & 0xff) * 16 + 700),
-		    ((int)((msr.hi >> 16) & 0xff) * 16 + 700),
-		    ((int)(msr.hi & 0xff) * 16 + 700));
-
-	printk(BIOS_INFO, "CPU multiplier: %dx (min %dx; max %dx)\n",
-		    (int)((msr.lo >> 8) & 0xff),
-		    (int)((msr.hi >> 24) & 0xff), (int)((msr.hi >> 8) & 0xff));
-
-	printk(BIOS_DEBUG, " msr.lo = %x\n", msr.lo);
-
-	/* Wait while CPU is busy */
-	cnt = 0;
-	while (msr.lo & ((1 << 16) | (1 << 17))) {
-		udelay(16);
-		msr = rdmsr(MSR_IA32_PERF_STATUS);
-		cnt++;
-		if (cnt > 128) {
-			printk(BIOS_WARNING, "Could not update multiplier and voltage.\n");
-			return;
-		}
-	}
-
-	current = msr.lo & 0xffff;
-
-	// Start out with no change.
-	new = current;
-	switch (model) {
-	case 10:		// model A
-		for (i = 0; i < ARRAY_SIZE(c7a_speed_translation); i += 2) {
-			if ((c7a_speed_translation[i] == current) &&
-			    ((c7a_speed_translation[i + 1] & 0xff00) ==
-			     (msr.hi & 0xff00))) {
-				new = c7a_speed_translation[i + 1];
-			}
-		}
-		break;
-	case 13:		// model D
-		for (i = 0; i < ARRAY_SIZE(c7d_speed_translation); i += 2) {
-			if ((c7d_speed_translation[i] == current) &&
-			    ((c7d_speed_translation[i + 1] & 0xff00) ==
-			     (msr.hi & 0xff00))) {
-				new = c7d_speed_translation[i + 1];
-			}
-		}
-		break;
-	default:
-		print_info("CPU type not known, multiplier unchanged.\n");
-	}
-
-	msr.lo = new;
-	msr.hi = 0;
-	printk(BIOS_DEBUG, " new msr.lo = %x\n", msr.lo);
-
-	wrmsr(MSR_IA32_PERF_CTL, msr);
-
-	/* Wait until the power transition ends */
-	cnt = 0;
-	do {
-		udelay(16);
-		msr = rdmsr(MSR_IA32_PERF_STATUS);
-		cnt++;
-		if (cnt > 128) {
-			printk(BIOS_WARNING, "Error while updating multiplier and voltage\n");
-			break;
-		}
-	} while (msr.lo & ((1 << 16) | (1 << 17)));
-
-	printk(BIOS_INFO, "Current voltage: %dmV\n", ((int)(msr.lo & 0xff) * 16 + 700));
-	printk(BIOS_INFO, "Current CPU multiplier: %dx\n", (int)((msr.lo >> 8) & 0xff));
-}
-
-static void model_c7_init(device_t dev)
-{
-	u8 brand;
-	struct cpuinfo_x86 c;
-	msr_t msr;
-
-	get_fms(&c, dev->device);
-
-	printk(BIOS_INFO, "Detected VIA ");
-
-	switch (c.x86_model) {
-	case 10:
-		msr = rdmsr(0x1153);
-		brand = (((msr.lo >> 2) ^ msr.lo) >> 18) & 3;
-		printk(BIOS_INFO, "Model A ");
-		break;
-	case 13:
-		msr = rdmsr(0x1154);
-		brand = (((msr.lo >> 4) ^ (msr.lo >> 2))) & 0x000000ff;
-		printk(BIOS_INFO, "Model D ");
-		break;
-	default:
-		printk(BIOS_INFO, "Model Unknown ");
-		brand = 0xff;
-	}
-
-	switch (brand) {
-	case 0:
-		printk(BIOS_INFO, "C7-M\n");
-		break;
-	case 1:
-		printk(BIOS_INFO, "C7\n");
-		break;
-	case 2:
-		printk(BIOS_INFO, "Eden\n");
-		break;
-	case 3:
-		printk(BIOS_INFO, "C7-D\n");
-		break;
-	default:
-		printk(BIOS_INFO, "%02x (please report)\n", brand);
-	}
-
-	/* Gear up */
-	set_c7_speed(c.x86_model);
-
-	/* Enable APIC */
-	msr = rdmsr(0x1107);
-	msr.lo |= 1<<24;
-	wrmsr(0x1107, msr);
-
-	/* Turn on cache */
-	x86_enable_cache();
-
-	/* Set up Memory Type Range Registers */
-	x86_setup_mtrrs();
-	x86_mtrr_check();
-
-	/* Enable the local cpu apics */
-	setup_lapic();
-};
-
-static struct device_operations cpu_dev_ops = {
-	.init = model_c7_init,
-};
-
-/* Look in arch/x86/lib/cpu.c:cpu_initialize. If there is no CPU with an exact
- * ID, the cpu mask (stepping) is masked out and the check is repeated. This
- * allows us to keep the table significantly smaller.
- */
-
-static struct cpu_device_id cpu_table[] = {
-	{X86_VENDOR_CENTAUR, 0x06A0},	// VIA C7 Esther
-	{X86_VENDOR_CENTAUR, 0x06A9},	// VIA C7 Esther
-	{X86_VENDOR_CENTAUR, 0x06D0},	// VIA C7-M
-	{0, 0},
-};
-
-static const struct cpu_driver driver __cpu_driver = {
-	.ops = &cpu_dev_ops,
-	.id_table = cpu_table,
-};
diff --git a/src/mainboard/bcom/winnetp680/devicetree.cb b/src/mainboard/bcom/winnetp680/devicetree.cb
index c86bc6a..3e31223 100644
--- a/src/mainboard/bcom/winnetp680/devicetree.cb
+++ b/src/mainboard/bcom/winnetp680/devicetree.cb
@@ -57,7 +57,7 @@ chip northbridge/via/cn700			# Northbridge
     end
   end
   device lapic_cluster 0 on			# APIC cluster
-    chip cpu/via/model_c7			# VIA C7
+    chip cpu/via/c7			# VIA C7
       device lapic 0 on end			# APIC
     end
   end
diff --git a/src/mainboard/jetway/j7f24/devicetree.cb b/src/mainboard/jetway/j7f24/devicetree.cb
index cbc45c3..16dd2f6 100644
--- a/src/mainboard/jetway/j7f24/devicetree.cb
+++ b/src/mainboard/jetway/j7f24/devicetree.cb
@@ -55,7 +55,7 @@ chip northbridge/via/cn700			# Northbridge
     end
   end
   device lapic_cluster 0 on			# APIC cluster
-    chip cpu/via/model_c7			# VIA C7
+    chip cpu/via/c7			# VIA C7
       device lapic 0 on end			# APIC
     end
   end
diff --git a/src/mainboard/via/epia-cn/devicetree.cb b/src/mainboard/via/epia-cn/devicetree.cb
index 727ccc5..96a2222 100644
--- a/src/mainboard/via/epia-cn/devicetree.cb
+++ b/src/mainboard/via/epia-cn/devicetree.cb
@@ -54,7 +54,7 @@ chip northbridge/via/cn700			# Northbridge
     end
   end
   device lapic_cluster 0 on			# APIC cluster
-    chip cpu/via/model_c7			# VIA C7
+    chip cpu/via/c7			# VIA C7
       device lapic 0 on end			# APIC
     end
   end
diff --git a/src/mainboard/via/epia-m/devicetree.cb b/src/mainboard/via/epia-m/devicetree.cb
index cc4a39d..3db72ee 100644
--- a/src/mainboard/via/epia-m/devicetree.cb
+++ b/src/mainboard/via/epia-m/devicetree.cb
@@ -1,7 +1,7 @@
 chip northbridge/via/vt8623
 
 	device lapic_cluster 0 on
-		chip cpu/via/model_c3
+		chip cpu/via/c3
 			device lapic 0 on  end
 		end
 	end
diff --git a/src/mainboard/via/epia-m700/devicetree.cb b/src/mainboard/via/epia-m700/devicetree.cb
index 4e8e2a8..a687f09 100644
--- a/src/mainboard/via/epia-m700/devicetree.cb
+++ b/src/mainboard/via/epia-m700/devicetree.cb
@@ -17,7 +17,7 @@ chip northbridge/via/vx800	# Northbridge
     # end
   end
   device lapic_cluster 0 on	# APIC cluster
-    chip cpu/via/model_c7	# VIA C7
+    chip cpu/via/c7	# VIA C7
       device lapic 0 on end	# APIC
     end
   end
diff --git a/src/mainboard/via/epia-n/devicetree.cb b/src/mainboard/via/epia-n/devicetree.cb
index 651a1a2..3505374 100644
--- a/src/mainboard/via/epia-n/devicetree.cb
+++ b/src/mainboard/via/epia-n/devicetree.cb
@@ -22,7 +22,7 @@
 chip northbridge/via/cn400			# Northbridge
 
   device lapic_cluster 0 on			# APIC cluster
-    chip cpu/via/model_c3			# VIA C3
+    chip cpu/via/c3			# VIA C3
       device lapic 0 on end			# APIC
     end
   end
diff --git a/src/mainboard/via/epia/devicetree.cb b/src/mainboard/via/epia/devicetree.cb
index b883e56..c906074 100644
--- a/src/mainboard/via/epia/devicetree.cb
+++ b/src/mainboard/via/epia/devicetree.cb
@@ -54,7 +54,7 @@ chip northbridge/via/vt8601
 	end
 
         device lapic_cluster 0 on
-                chip cpu/via/model_c3
+                chip cpu/via/c3
                         device lapic 0 on end
                 end
         end
diff --git a/src/mainboard/via/pc2500e/devicetree.cb b/src/mainboard/via/pc2500e/devicetree.cb
index 05ce877..bb3ddcc 100644
--- a/src/mainboard/via/pc2500e/devicetree.cb
+++ b/src/mainboard/via/pc2500e/devicetree.cb
@@ -82,7 +82,7 @@ chip northbridge/via/cn700			# Northbridge
     end
   end
   device lapic_cluster 0 on			# APIC cluster
-    chip cpu/via/model_c7			# VIA C7
+    chip cpu/via/c7			# VIA C7
       device lapic 0 on end			# APIC
     end
   end
diff --git a/src/mainboard/via/vt8454c/devicetree.cb b/src/mainboard/via/vt8454c/devicetree.cb
index 1a5bf54..ab09071 100644
--- a/src/mainboard/via/vt8454c/devicetree.cb
+++ b/src/mainboard/via/vt8454c/devicetree.cb
@@ -1,6 +1,6 @@
 chip northbridge/via/cx700
 	device lapic_cluster 0 on
-		chip cpu/via/model_c7
+		chip cpu/via/c7
 			device lapic 0 on end
 		end
 	end




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