[coreboot] How to port core boot

ali hagigat hagigatali at gmail.com
Tue Feb 7 16:25:13 CET 2012

Thank you Rudolf  for the reply. 1M to 3M is OK please look at the
serial port output:

coreboot-4.0-1959-g950f20a-dirty Tue Feb  7 18:39:18 IRST 2012 starting...
Testing DRAM : 00100000 - 00900000
DRAM fill: 0x00100000-0x00900000
DRAM filled
DRAM verify: 0x00100000-0x00900000
DRAM range verified.
Loading image.
Searching for fallback/coreboot_ram
Check fallback/romstage
Check fallback/coreboot_ram
Stage: loading fallback/coreboot_ram @ 0x100000 (180224 bytes), entry @ 0x100000
Stage: done loading.
Jumping to image.

On Tue, Feb 7, 2012 at 3:07 AM, Rudolf Marek <r.marek at assembler.cz> wrote:
>> Seems there is a case or two of possible infinite while() loops within
>> the uart8250 serial console code. This is a wild guess, but the uart
> Yeah I dont like that too. Maybe worth to do a timeout? Or Loop count? It is
> always better to boot than to have perfect serial output ;)
> But in this case I would think memory is not 100% OK. Worth to check if
> 1M->3M is OK (this is where coreboot ramstage goes)
> Thanks
> Rudolf
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