[coreboot] How to port core boot

Kyösti Mälkki kyosti.malkki at gmail.com
Mon Feb 6 20:21:08 CET 2012

On Mon, 2012-02-06 at 19:17 +0330, ali hagigat wrote:
> I can verify that by the assembly code i have. writing to any memory
> location and reading that. Also I tested it by ram_check()
> in Coreboot. Both are correct.
> The last post codes are 0x39, 0x80 and Coreboot seems to stop!


0x80 seems like a reasonable POST from the very beginning of stage
coreboot_ram. Continue your work with src/boot/hardwaremain.c; figure
out whether you only lose serial communication or if the execution
actually halts.

Seems there is a case or two of possible infinite while() loops within
the uart8250 serial console code. This is a wild guess, but the uart
could end up in a bad state if transmit buffers are non-empty while
divisors are programmed etc. Maybe raise the speed to more common and
tested 115200.


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