[coreboot] Patch set updated for coreboot: 44e8b03 SIO: Add smsc/sch4037 superio support

She, Kerry Kerry.She at amd.com
Fri Feb 3 11:17:53 CET 2012


Dear Paul,

Thanks for your careful review,
I have fix these problem, and upload a new patch set.
Thanks
--Kerry

> -----Original Message-----
> From: Paul Menzel [mailto:paulepanter at users.sourceforge.net]
> Sent: Friday, February 03, 2012 5:21 PM
> To: coreboot at coreboot.org
> Cc: She, Kerry; Kerry Sheh
> Subject: Re: [coreboot] Patch set updated for coreboot: 44e8b03 SIO: Add
> smsc/sch4037 superio support
> 
> Dear Kerry,
> 
> 
> thank you for updating the patch.
> 
> 
> Am Freitag, den 03.02.2012, 04:28 +0100 schrieb Kerry Sheh:
> > Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to
> > gerrit, which you can find at http://review.coreboot.org/562
> >
> > -gerrit
> >
> > commit 44e8b03e634c0b236dc7f252104c2399757c6145
> > Author: Kerry Sheh <shekairui at gmail.com>
> > Date:   Fri Feb 3 12:23:58 2012 +0800
> >
> >     SIO: Add smsc/sch4037 superio support
> >
> >     Change-Id: I3b113a27541b8efd096f3bd44e6621344ec916a5
> >     Signed-off-by: Kerry Sheh <kerry.she at amd.com>
> >     Signed-off-by: Kerry Sheh <shekairui at gmail.com>
> > ---
> >  src/superio/smsc/Kconfig                      |    3 +
> >  src/superio/smsc/Makefile.inc                 |    2 +
> >  src/superio/smsc/sch4037/Makefile.inc         |   20 ++++
> >  src/superio/smsc/sch4037/chip.h               |   34 +++++++
> >  src/superio/smsc/sch4037/sch4037.h            |   34 +++++++
> >  src/superio/smsc/sch4037/sch4037_early_init.c |   71 ++++++++++++++
> >  src/superio/smsc/sch4037/superio.c            |  123
> +++++++++++++++++++++++++
> >  7 files changed, 287 insertions(+), 0 deletions(-)
> 
> […]
> 
> > diff --git a/src/superio/smsc/sch4037/sch4037_early_init.c
> > b/src/superio/smsc/sch4037/sch4037_early_init.c
> > new file mode 100644
> > index 0000000..392f229
> > --- /dev/null
> > +++ b/src/superio/smsc/sch4037/sch4037_early_init.c
> > @@ -0,0 +1,71 @@
> > +/*
> > + * This file is part of the coreboot project.
> > + *
> > + * Copyright (C) 2012 Advanced Micro Devices, Inc.
> > + *
> > + * This program is free software; you can redistribute it and/or
> > +modify
> > + * it under the terms of the GNU General Public License as published
> > +by
> > + * the Free Software Foundation; version 2 of the License.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
> > +02110-1301 USA  */
> > +
> > +/* Pre-RAM driver for the SMSC KBC1100 Super I/O chip */
> 
> Is that comment still valid? I think the model number needs to be updated.
> 
> > +
> > +#include <arch/romcc_io.h>
> > +#include "sch4037.h"
> > +
> > +static inline void pnp_enter_conf_state(device_t dev) {
> > +	unsigned port = dev>>8;
> > +	outb(0x55, port);
> > +}
> > +
> > +static void pnp_exit_conf_state(device_t dev) {
> > +	unsigned port = dev>>8;
> > +	outb(0xaa, port);
> > +}
> > +
> > +static inline void sch4037_early_init(unsigned port) {
> > +	device_t dev;
> > +
> > +	dev = PNP_DEV (port, SMSCSUPERIO_SP1);
> > +	pnp_enter_conf_state(dev);
> > +
> > +	/*Auto power management*/
> 
> For consistency spaces are missing at the borders.
> 
> > +	pnp_write_config (dev, 0x22, 0x38); /* BIT3+BIT4+BIT5 */
> > +	pnp_write_config (dev, 0x23, 0 );
> > +
> > +	/* Enable SMSC UART 0 */
> > +	dev = PNP_DEV (port, SMSCSUPERIO_SP1);
> > +	pnp_set_logical_device(dev);
> > +	pnp_set_enable(dev, 0);
> > +
> > +	pnp_set_iobase(dev, PNP_IDX_IO0, CONFIG_TTYS0_BASE);
> > +	pnp_set_irq(dev, PNP_IDX_IRQ0, 0x4);
> > +
> > +	/* Enabled High speed, disabled MIDI support. */
> > +	pnp_write_config (dev, 0xF0, 0x02);
> > +	pnp_set_enable(dev, 1);
> > +
> > +	/* Enable keyboard */
> > +	dev = PNP_DEV (port, SCH4037_KBC);
> > +	pnp_set_logical_device(dev);
> > +	pnp_set_enable(dev, 0);
> > +	pnp_set_irq(dev, 0x70, 1);   /* IRQ 1 */
> > +	pnp_set_irq(dev, 0x72, 12);   /* IRQ 12 */
> > +	pnp_set_enable(dev, 1);
> > +
> > +	pnp_exit_conf_state(dev);
> > +
> > +}
> > +
> > diff --git a/src/superio/smsc/sch4037/superio.c
> > b/src/superio/smsc/sch4037/superio.c
> > new file mode 100644
> > index 0000000..af4040f
> > --- /dev/null
> > +++ b/src/superio/smsc/sch4037/superio.c
> > @@ -0,0 +1,123 @@
> > +/*
> > + * This file is part of the coreboot project.
> > + *
> > + * Copyright (C) 2012 Advanced Micro Devices, Inc.
> > + *
> > + * This program is free software; you can redistribute it and/or
> > +modify
> > + * it under the terms of the GNU General Public License as published
> > +by
> > + * the Free Software Foundation; version 2 of the License.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
> > +02110-1301 USA  */
> > +
> > +/* RAM driver for the SMSC KBC1100 Super I/O chip */
> 
> Dito.
> 
> […]
> 
> 
> Thanks,
> 
> Paul


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