No subject

Sun Dec 9 17:34:17 CET 2012

19.[0123] and other processor devices all live on PCI bus 0? Is that bus
somewhat related to the buses attached via ncHT? IIRC I once saw a
machine where 18.[0123] was alone on bus 0 and all other PCI devices
were on separate buses.

Taking the "everything is PCI" model, how would I specify the virtual
PCI buses attached via ncHT? Are they children (secondary buses) of 18.0
which would act like a PCI-to-PCI bridge?

> The dts should be easy for people to fill in to make a platform work.


> They don't know (or need to know) what ht links are connecting the cpu
> and what ones go to pci bus.

They need a way to specify settings for any given PCI device. Since most
modern machines have multiple PCI devices with the same vendor/device
ID, we have to be able to identify devices based on their logical path.
For that, we have to model the logical PCI bus/device/tree reasonably
well. I'm trying to do that, but no model seems to fit.



More information about the coreboot mailing list