CPU core glued to an Intel 3100 northbridge/southbridge/SuperIO, with a slightly fancier DDR2 memory controller. Thus my patches augment the existing Intel 3100 code in coreboot. The code was written using information in the datasheet available on the Intel web site, and has been tested on an EP80579 Development Board (codename "Truxton"), booting a Linux 2.6.25.1 kernel payload. --Ed