[coreboot] Patch merged into coreboot/master: 3bf9ed1 Make the device tree available in the rom stage

gerrit at coreboot.org gerrit at coreboot.org
Sat Aug 4 18:05:40 CEST 2012

the following patch was just integrated into master:
commit 3bf9ed165efd91cb8d51e42e71528c140b4caf15
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Tue Jul 31 16:47:25 2012 -0700

    Make the device tree available in the rom stage
    We thought about two ways to do this change. The way we decided to try
    was to
    1. drop all ops from devices in romstage
    2. constify all devices in romstage (make them read-only) so we can
       compile static.c into romstage
    3. the device tree "devices" can be used to read configuration from
       the device tree (and nothing else, really)
    4. the device tree devices are accessed through struct device * in
       romstage only. device_t stays the typedef to int in romstage
    5. Use the same static.c file in ramstage and romstage
    We declare structs as follows:
    ROMSTAGE_CONST struct bus dev_root_links[];
    ROMSTAGE_CONST is const in romstage and empty in ramstage; This
    forces all of the device tree into the text area.
    So a struct looks like this:
    static ROMSTAGE_CONST struct device _dev21 = {
     #ifndef __PRE_RAM__
            .ops = 0,
            .bus = &_dev7_links[0],
            .path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x1c,3)}}},
            .enabled = 0,
            .on_mainboard = 1,
            .subsystem_vendor = 0x1ae0,
            .subsystem_device = 0xc000,
            .link_list = NULL,
            .sibling = &_dev22,
     #ifndef __PRE_RAM__
            .chip_ops = &southbridge_intel_bd82x6x_ops,
            .chip_info = &southbridge_intel_bd82x6x_info_10,
    Change-Id: I722454d8d3c40baf7df989f5a6891f6ba7db5727
    Signed-off-by: Ronald G. Minnich <rminnich at chromium.org>
    Signed-off-by: Stefan Reinauer <reinauer at google.com>

Build-Tested: build bot (Jenkins) at Sat Aug  4 00:06:15 2012, giving +1
Reviewed-By: Ronald G. Minnich <rminnich at gmail.com> at Sat Aug  4 18:05:34 2012, giving +2
See http://review.coreboot.org/1398 for details.


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