[coreboot] New patch to review for coreboot: cbe5a5b AMD NB: Limit the device field to 5 bits. (Propagation)

Zheng Bao (zheng.bao@amd.com) gerrit at coreboot.org
Fri Aug 3 07:59:15 CEST 2012


Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1403

-gerrit

commit cbe5a5b90010158d78913f83817390e332894eae
Author: zbao <fishbaozi at gmail.com>
Date:   Fri Aug 3 15:44:42 2012 +0800

    AMD NB: Limit the device field to 5 bits. (Propagation)
    
    Apply the change
    http://review.coreboot.org/1264
    to all the AMD northbridge.
    
    Change-Id: Ied74d6f579d2c0350288e2619d7810f8d44fa574
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: zbao <fishbaozi at gmail.com>
---
 src/northbridge/amd/agesa/family10/northbridge.c |    4 ++--
 src/northbridge/amd/agesa/family12/northbridge.c |    6 +++++-
 src/northbridge/amd/agesa/family14/northbridge.c |    6 +++++-
 src/northbridge/amd/agesa/family15/northbridge.c |    4 ++--
 src/northbridge/amd/amdfam10/northbridge.c       |    4 ++--
 5 files changed, 16 insertions(+), 8 deletions(-)

diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c
index 831aec0..8cc9475 100644
--- a/src/northbridge/amd/agesa/family10/northbridge.c
+++ b/src/northbridge/amd/agesa/family10/northbridge.c
@@ -361,8 +361,8 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
 
 static device_t get_node_pci(u32 nodeid, u32 fn)
 {
-#if NODE_NUMS == 64
-	if (nodeid < 32) {
+#if NODE_NUMS + CONFIG_CDB >= 32
+	if ((CONFIG_CDB + nodeid) < 32) {
 		return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
 	} else {
 		return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn));
diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c
index f3f03a4..af1d4f0 100644
--- a/src/northbridge/amd/agesa/family12/northbridge.c
+++ b/src/northbridge/amd/agesa/family12/northbridge.c
@@ -50,7 +50,11 @@ static unsigned fx_devs=0;
 
 device_t get_node_pci(u32 nodeid, u32 fn)
 {
-    return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
+	if ((CONFIG_CDB + nodeid) < 32) {
+		return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
+	} else {
+		return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn));
+	}
 }
 
 
diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c
index af6dfcc..a03939c 100644
--- a/src/northbridge/amd/agesa/family14/northbridge.c
+++ b/src/northbridge/amd/agesa/family14/northbridge.c
@@ -51,7 +51,11 @@ static unsigned fx_devs = 0;
 
 device_t get_node_pci(u32 nodeid, u32 fn)
 {
-	return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
+	if ((CONFIG_CDB + nodeid) < 32) {
+		return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
+	} else {
+		return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn));
+	}
 }
 
 static void get_fx_devs(void)
diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c
index a080293..8d64a30 100644
--- a/src/northbridge/amd/agesa/family15/northbridge.c
+++ b/src/northbridge/amd/agesa/family15/northbridge.c
@@ -122,8 +122,8 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
 
 static device_t get_node_pci(u32 nodeid, u32 fn)
 {
-#if MAX_NODE_NUMS == 64
-	if (nodeid < 32) {
+#if MAX_NODE_NUMS + CONFIG_CDB >= 32
+	if ((CONFIG_CDB + nodeid) < 32) {
 		return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
 	} else {
 		return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn));
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index 15b29f6..aa15fdd 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -63,8 +63,8 @@ static unsigned fx_devs=0;
 
 device_t get_node_pci(u32 nodeid, u32 fn)
 {
-#if NODE_NUMS == 64
-	if(nodeid<32) {
+#if NODE_NUMS + CONFIG_CDB >= 32
+	if((CONFIG_CDB + nodeid) < 32) {
 		return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
 	} else {
 		return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn));




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