[coreboot] New patch to review for coreboot: 8452211 SuperIO LPC47N217: Remove warnings

Zheng Bao (zheng.bao@amd.com) gerrit at coreboot.org
Fri Aug 3 07:23:51 CEST 2012


Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1402

-gerrit

commit 8452211aaea71a5b01b22708fa606e653f336d11
Author: zbao <fishbaozi at gmail.com>
Date:   Fri Aug 3 15:09:09 2012 +0800

    SuperIO LPC47N217: Remove warnings
    
    Change-Id: Id5756f1bb748ae7bec0bcdc21804f5338e850baa
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: zbao <fishbaozi at gmail.com>
---
 src/superio/smsc/lpc47n217/early_serial.c |    4 ++--
 src/superio/smsc/lpc47n217/superio.c      |    7 ++++---
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/src/superio/smsc/lpc47n217/early_serial.c b/src/superio/smsc/lpc47n217/early_serial.c
index ce79db8..d767e05 100644
--- a/src/superio/smsc/lpc47n217/early_serial.c
+++ b/src/superio/smsc/lpc47n217/early_serial.c
@@ -42,7 +42,7 @@ static void pnp_exit_conf_state(device_t dev)
  * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number.
  * @param iobase Base I/O port for the logical device.
  */
-void lpc47n217_pnp_set_iobase(device_t dev, u16 iobase)
+static void lpc47n217_pnp_set_iobase(device_t dev, u16 iobase)
 {
 	/* LPC47N217 requires base ports to be a multiple of 4. */
 	ASSERT(!(iobase & 0x3));
@@ -74,7 +74,7 @@ void lpc47n217_pnp_set_iobase(device_t dev, u16 iobase)
  * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number.
  * @param enable 0 to disable, anythig else to enable.
  */
-void lpc47n217_pnp_set_enable(device_t dev, int enable)
+static void lpc47n217_pnp_set_enable(device_t dev, int enable)
 {
 	u8 power_register = 0, power_mask = 0, current_power, new_power;
 
diff --git a/src/superio/smsc/lpc47n217/superio.c b/src/superio/smsc/lpc47n217/superio.c
index 88832e1..01c96b1 100644
--- a/src/superio/smsc/lpc47n217/superio.c
+++ b/src/superio/smsc/lpc47n217/superio.c
@@ -133,7 +133,8 @@ static void lpc47n217_pnp_enable(device_t dev)
  */
 static void lpc47n217_init(device_t dev)
 {
-	struct superio_smsc_lpc47n217_config* conf = dev->chip_info;
+	/* TODO: Reserved for future. */
+	/* struct superio_smsc_lpc47n217_config* conf = dev->chip_info; */
 
 	if (!dev->enabled)
 		return;
@@ -142,7 +143,7 @@ static void lpc47n217_init(device_t dev)
 static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource)
 {
 	if (!(resource->flags & IORESOURCE_ASSIGNED)) {
-		printk(BIOS_ERR, "ERROR: %s %02x not allocated\n",
+		printk(BIOS_ERR, "ERROR: %s %02lx not allocated\n",
 		       dev_path(dev), resource->index);
 		return;
 	}
@@ -160,7 +161,7 @@ static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource)
 	} else if (resource->flags & IORESOURCE_IRQ) {
 		lpc47n217_pnp_set_irq(dev, resource->base);
 	} else {
-		printk(BIOS_ERR, "ERROR: %s %02x unknown resource type\n",
+		printk(BIOS_ERR, "ERROR: %s %02lx unknown resource type\n",
 		       dev_path(dev), resource->index);
 		return;
 	}




More information about the coreboot mailing list