[coreboot] Patch merged into coreboot/master: 2785a0c AMD F15tn northbridge: Remove the misleading 0x100 from the limitk.

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 2785a0c0c64b140a1e0a57ca060b7b4d193a91e5
Author: zbao <fishbaozi at gmail.com>
Date:   Wed Aug 1 18:23:49 2012 +0800

    AMD F15tn northbridge: Remove the misleading 0x100 from the limitk.
    
    I dont known if missed something, but why an extra 0x100 was added to limit?
    My board would get the wrong memory table entry 7f000000-7fffffff as RAM, which
    is higher than TOM.
    coreboot memory table:
    0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
    1. 0000000000001000-000000000009ffff: RAM
    2. 00000000000c0000-000000005e13efff: RAM
    3. 000000005e13f000-000000005effffff: CONFIGURATION TABLES
    4. 000000005f000000-000000007effffff: RESERVED
    5. 000000007f000000-000000007fffffff: RAM
    6. 00000000a0000000-00000000afffffff: RESERVED
    
    Ronald G. Minnich:
     I think someone who wrote the code was trying to round up the
    next 0x100 boundary and did it incorrectly.
    Here is code that would do it correctly:
    limitk = ((resource_t)((d.mask + 0x00000ff) & 0x1fffff00)) << 9 ;
    
    Zheng:
     Plus 0xFF is correct, but the d.mask take bit 0 as enable it.
    This bit should be clear when we try to calculate the limitk.
    
    Change-Id: I3848ed5f23001e5bd61a19833650fe13df26eef3
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: zbao <fishbaozi at gmail.com>

Build-Tested: build bot (Jenkins) at Wed Aug  1 10:55:35 2012, giving +1
Reviewed-By: Ronald G. Minnich <rminnich at gmail.com> at Wed Aug  1 17:24:04 2012, giving +2
See http://review.coreboot.org/1265 for details.

-gerrit