[coreboot] New patch to review for coreboot: 4fe7af0 Fix whitespace for ma785gm

[Alec Ari (neotheuser@ymail.com)]

Alec Ari (neotheuser at ymail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/923

-gerrit

commit 4fe7af04db174d448dc26b9db44f7872587ab533
Author: Alec Ari <neotheuser at ymail.com>
Date:   Mon Apr 23 20:24:24 2012 -0500

    Fix whitespace for ma785gm
    
    Fix tabs and whitespace for
    ma785gm mainboard.c file.
    
    Change-Id: I8c94bf428bc4e78871da8c64f89221af4151e16d
    Signed-off-by: Alec Ari <neotheuser at ymail.com>
---
 src/mainboard/gigabyte/ma785gm/mainboard.c |   22 +++++++++++-----------
 1 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/src/mainboard/gigabyte/ma785gm/mainboard.c b/src/mainboard/gigabyte/ma785gm/mainboard.c
index 97a86f6..989dfb5 100644
--- a/src/mainboard/gigabyte/ma785gm/mainboard.c
+++ b/src/mainboard/gigabyte/ma785gm/mainboard.c
@@ -91,7 +91,7 @@ void set_pcie_reset()
  */
 int is_dev3_present(void)
 {
-		return 0;
+	return 0;
 }
 
 /*
@@ -122,16 +122,16 @@ static void set_gpio40_gfx(void)
 	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
 
 	/* set the gfx to 1x16 lanes */
-		printk(BIOS_INFO, "Dev3 is not present. GFX Configuration is One x16 slot\n");
-		/* when the gpio40 is configured as GPIO, this will enable the output */
-		pci_write_config32(sm_dev, 0xf8, 0x4);
-		dword = pci_read_config32(sm_dev, 0xfc);
-		dword &= ~(1 << 10);
-
-        	/* When the gpio40 is configured as GPIO, this will represent the output value*/
-		/* 1 :enable two x8  , 0 : master slot enable only */
-		dword &=  ~(1 << 26);
-		pci_write_config32(sm_dev, 0xfc, dword);
+	printk(BIOS_INFO, "Dev3 is not present. GFX Configuration is One x16 slot\n");
+	/* when the gpio40 is configured as GPIO, this will enable the output */
+	pci_write_config32(sm_dev, 0xf8, 0x4);
+	dword = pci_read_config32(sm_dev, 0xfc);
+	dword &= ~(1 << 10);
+
+        /* When the gpio40 is configured as GPIO, this will represent the output value*/
+	/* 1 :enable two x8  , 0 : master slot enable only */
+	dword &=  ~(1 << 26);
+	pci_write_config32(sm_dev, 0xfc, dword);
 }
 
 /*************************************************