[coreboot] Patch set updated for coreboot: 9398cfc Unbreak boards where chipset can select between FSB and serial APIC bus

Peter Stuge (peter@stuge.se) gerrit at coreboot.org
Mon Apr 23 00:14:49 CEST 2012

Peter Stuge (peter at stuge.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/921


commit 9398cfcac1da9342e94a574e4c31c9e0b65198fd
Author: Rudolf Marek <r.marek at assembler.cz>
Date:   Sun Apr 22 23:52:23 2012 +0200

    Unbreak boards where chipset can select between FSB and serial APIC bus
    Commit d4d5e4d3e10da06a83d57a147bd58a733381de18 contains #ifdef instead
    of #if, making the FSB/serial bus selection for APIC always select serial
    bus. The bug is harmless on most chipsets because the bit is often RO,
    but it breaks at least on VIA K8T890.
    Change-Id: I89c4855922199eca7f921c3e4eb500656544c8e5
    Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
 src/arch/x86/lib/ioapic.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/arch/x86/lib/ioapic.c b/src/arch/x86/lib/ioapic.c
index e974d7c..57b99e2 100644
--- a/src/arch/x86/lib/ioapic.c
+++ b/src/arch/x86/lib/ioapic.c
@@ -89,7 +89,7 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id)
 		ioapic_interrupts = 24;
 	printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts);
 	 * For the Pentium 4 and above APICs deliver their interrupts
 	 * on the front side bus, enable that.
@@ -98,7 +98,7 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id)
 	io_apic_write(ioapic_base, 0x03,
 		      io_apic_read(ioapic_base, 0x03) | (1 << 0));
 	printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on APIC serial bus\n");
 	io_apic_write(ioapic_base, 0x03, 0);

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