[coreboot] Patch set updated for coreboot: 58f3030 Add Southbridge support for S3.
Zheng Bao (zheng.bao@amd.com)
gerrit at coreboot.org
Thu Apr 5 06:11:23 CEST 2012
Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/621
-gerrit
commit 58f3030964d6ae7d446bd84c4bd3bd97481061a8
Author: zbao <fishbaozi at gmail.com>
Date: Thu Apr 5 13:18:49 2012 +0800
Add Southbridge support for S3.
1. Add some CIMX call for S3.
2. Detect sleep type.
Change-Id: I62888e8d8a03987ca88f5c935fa660f6b49a4fe9
Signed-off-by: Zheng Bao <zheng.bao at amd.com>
Signed-off-by: zbao <fishbaozi at gmail.com>
---
src/southbridge/amd/Makefile.inc | 11 +++++
src/southbridge/amd/cimx/sb800/SBPLATFORM.h | 3 +
src/southbridge/amd/cimx/sb800/cfg.c | 61 +++++++++++++++++++++++----
src/southbridge/amd/cimx/sb800/early.c | 8 ++++
src/southbridge/amd/cimx/sb800/late.c | 19 ++++++++
src/southbridge/amd/cimx/sb800/lpc.c | 4 +-
src/southbridge/amd/cimx/sb800/lpc.h | 1 -
src/southbridge/amd/cimx/sb800/sb_cimx.h | 4 ++
8 files changed, 100 insertions(+), 11 deletions(-)
diff --git a/src/southbridge/amd/Makefile.inc b/src/southbridge/amd/Makefile.inc
index 65e4729..2cdca29 100644
--- a/src/southbridge/amd/Makefile.inc
+++ b/src/southbridge/amd/Makefile.inc
@@ -15,3 +15,14 @@ subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += cimx
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += cimx
+$(obj)/s3.rom:
+ echo " S3 NVRAM 0xffff0000 (S3 storage area)"
+ echo -ne '\xFF' > $@
+ for ((i=0;i<20479;i++)) do echo -ne '\xFF' >> $@ ; done
+
+ifeq ($(CONFIG_HAVE_ACPI_RESUME), y)
+cbfs-files-y += s3nv
+s3nv-file := $(obj)/s3.rom
+s3nv-position := 0xffff0000
+s3nv-type := raw
+endif
diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
index 25aba95..7dc752a 100644
--- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
+++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
@@ -162,4 +162,7 @@ typedef union _PCI_ADDR {
#include "spi.h"
#endif
+#define BIOSRAM_INDEX 0xcd4
+#define BIOSRAM_DATA 0xcd5
+
#endif // _AMD_SBPLATFORM_H_
diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c
index a9e35bc..2b73155 100644
--- a/src/southbridge/amd/cimx/sb800/cfg.c
+++ b/src/southbridge/amd/cimx/sb800/cfg.c
@@ -17,10 +17,52 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-
+#include <console/console.h>
#include "SBPLATFORM.h"
#include "cfg.h"
+#include "OEM.h"
+#include <cbmem.h>
+
+#include <arch/io.h>
+#include <arch/acpi.h>
+
+#if CONFIG_HAVE_ACPI_RESUME == 1
+int acpi_get_sleep_type(void)
+{
+ u16 tmp = inw(PM1_CNT_BLK_ADDRESS);
+ tmp = ((tmp & (7 << 10)) >> 10);
+ printk(BIOS_DEBUG, "SLP_TYP type was %x\n", tmp);
+ return (int)tmp;
+}
+#endif
+
+#ifndef __PRE_RAM__
+void set_cbmem_toc(struct cbmem_entry *toc)
+{
+ u32 dword = (u32) toc;
+ int nvram_pos = 0xf8, i; /* temp */
+ printk(BIOS_DEBUG, "dword=%x\n", dword);
+ for (i = 0; i<4; i++) {
+ printk(BIOS_DEBUG, "nvram_pos=%x, dword>>(8*i)=%x\n", nvram_pos, (dword >>(8 * i)) & 0xff);
+ outb(nvram_pos, BIOSRAM_INDEX);
+ outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA);
+ nvram_pos++;
+ }
+}
+#endif
+struct cbmem_entry *get_cbmem_toc(void)
+{
+ u32 xdata = 0;
+ int xnvram_pos = 0xf8, xi;
+ for (xi = 0; xi<4; xi++) {
+ outb(xnvram_pos, BIOSRAM_INDEX);
+ xdata &= ~(0xff << (xi * 8));
+ xdata |= inb(BIOSRAM_DATA) << (xi *8);
+ xnvram_pos++;
+ }
+ return (struct cbmem_entry *) xdata;
+}
/**
* @brief South Bridge CIMx configuration
@@ -30,10 +72,13 @@
*/
void sb800_cimx_config(AMDSBCFG *sb_config)
{
- if (!sb_config) {
+ if (!sb_config)
return;
- }
- //memset(sb_config, 0, sizeof(AMDSBCFG));
+
+#if CONFIG_HAVE_ACPI_RESUME == 1
+ if (acpi_get_sleep_type() == 3)
+ sb_config->S3Resume = 1;
+#endif
/* header */
sb_config->StdHeader.PcieBasePtr = PCIEX_BASE_ADDRESS;
@@ -75,19 +120,19 @@ void sb800_cimx_config(AMDSBCFG *sb_config)
/* USB */
sb_config->USBMODE.UsbModeReg = USB_CONFIG;
- sb_config->SbUsbPll = 0;
+ sb_config->SbUsbPll = 0;
/* SATA */
sb_config->SataClass = SATA_MODE;
sb_config->SataIdeMode = SATA_IDE_MODE;
sb_config->SataPortMultCap = SATA_PORT_MULT_CAP_RESERVED;
- sb_config->SATAMODE.SataMode.SataController = SATA_CONTROLLER;
+ sb_config->SATAMODE.SataMode.SataController = SATA_CONTROLLER;
sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary, 1 -IDE as secondary.
//TODO: set to secondary not take effect.
sb_config->SATAMODE.SataMode.SataIdeCombinedMode = CONFIG_IDE_COMBINED_MODE;
sb_config->SATAMODE.SataMode.SATARefClkSel = SATA_CLOCK_SOURCE;
- /* Azalia HDA */
+ /* Azalia HDA */
sb_config->AzaliaController = AZALIA_CONTROLLER;
sb_config->AzaliaPinCfg = AZALIA_PIN_CONFIG;
sb_config->AZALIACONFIG.AzaliaSdinPin = AZALIA_SDIN_PIN;
@@ -97,7 +142,6 @@ void sb800_cimx_config(AMDSBCFG *sb_config)
#else
sb_config->AZOEMTBL.pAzaliaOemCodecTablePtr = NULL;
#endif
-
/* LPC */
/* SuperIO hardware monitor register access */
sb_config->SioHwmPortEnable = CONFIG_SB_SUPERIO_HWM;
@@ -132,4 +176,3 @@ void sb800_cimx_config(AMDSBCFG *sb_config)
}
#endif //!__PRE_RAM__
}
-
diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c
index 9d49a52..f692897 100644
--- a/src/southbridge/amd/cimx/sb800/early.c
+++ b/src/southbridge/amd/cimx/sb800/early.c
@@ -23,9 +23,11 @@
#include <device/pci_ids.h>
#include <arch/io.h> /* inl, outl */
#include <arch/romcc_io.h> /* device_t */
+#include <arch/acpi.h>
#include "SBPLATFORM.h"
#include "sb_cimx.h"
#include "cfg.h" /*sb800_cimx_config*/
+#include "cbmem.h"
#if CONFIG_RAMINIT_SYSINFO == 1
@@ -80,3 +82,9 @@ void sb800_clk_output_48Mhz(void)
*(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) |= 1 << 1; /* 48Mhz */
}
+#if CONFIG_HAVE_ACPI_RESUME == 1
+int acpi_is_wakeup_early(void)
+{
+ return (acpi_get_sleep_type() == 3);
+}
+#endif
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index 8c7abdb..c69782b 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -24,6 +24,7 @@
#include <arch/ioapic.h>
#include <device/smbus.h> /* smbus_bus_operations */
#include <console/console.h> /* printk */
+#include <arch/acpi.h>
#include "lpc.h" /* lpc_read_resources */
#include "SBPLATFORM.h" /* Platfrom Specific Definitions */
#include "cfg.h" /* sb800 Cimx configuration */
@@ -351,6 +352,17 @@ void sb_Late_Post(void)
AmdSbDispatcher(sb_config);
}
+void sb_Before_Pci_Restore_Init(void)
+{
+ sb_config->StdHeader.Func = SB_BEFORE_PCI_RESTORE_INIT;
+ AmdSbDispatcher(sb_config);
+}
+
+void sb_After_Pci_Restore_Init(void)
+{
+ sb_config->StdHeader.Func = SB_AFTER_PCI_RESTORE_INIT;
+ AmdSbDispatcher(sb_config);
+}
/**
* @brief SB Cimx entry point sbBeforePciInit wrapper
@@ -468,7 +480,14 @@ static void sb800_enable(device_t dev)
/* call the CIMX entry at the last sb800 device,
* so make sure the mainboard devicetree is complete
*/
+#if CONFIG_HAVE_ACPI_RESUME == 1
+ if (acpi_slp_type != 3)
+ sb_Before_Pci_Init();
+ else
+ sb_Before_Pci_Restore_Init();
+#else
sb_Before_Pci_Init();
+#endif
break;
default:
diff --git a/src/southbridge/amd/cimx/sb800/lpc.c b/src/southbridge/amd/cimx/sb800/lpc.c
index bc643b5..472817d 100644
--- a/src/southbridge/amd/cimx/sb800/lpc.c
+++ b/src/southbridge/amd/cimx/sb800/lpc.c
@@ -20,7 +20,9 @@
#include <console/console.h>
#include <device/pci.h>
#include "lpc.h"
-
+#include <bitops.h>
+#include <arch/io.h>
+#include <cbmem.h>
void lpc_read_resources(device_t dev)
{
diff --git a/src/southbridge/amd/cimx/sb800/lpc.h b/src/southbridge/amd/cimx/sb800/lpc.h
index 7b165f8..3d6a17a 100644
--- a/src/southbridge/amd/cimx/sb800/lpc.h
+++ b/src/southbridge/amd/cimx/sb800/lpc.h
@@ -20,7 +20,6 @@
#ifndef _SB800_LPC_H_
#define _SB800_LPC_H_
-
#define SPIROM_BASE_ADDRESS 0xA0 /* SPI ROM base address */
void lpc_read_resources(device_t dev);
diff --git a/src/southbridge/amd/cimx/sb800/sb_cimx.h b/src/southbridge/amd/cimx/sb800/sb_cimx.h
index 42a7ba9..5e510de 100644
--- a/src/southbridge/amd/cimx/sb800/sb_cimx.h
+++ b/src/southbridge/amd/cimx/sb800/sb_cimx.h
@@ -29,6 +29,10 @@ void sb_Before_Pci_Init(void);
void sb_After_Pci_Init(void);
void sb_Mid_Post_Init(void);
void sb_Late_Post(void);
+void sb_Before_Pci_Restore_Init(void);
+void sb_After_Pci_Restore_Init(void);
+
+int acpi_is_wakeup_early(void);
/**
* CIMX not set the clock to 48Mhz until sbBeforePciInit,
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