[coreboot] PCI target burst mode

[Nathan Williams]

Hi,

On our Geos boards (AMD Geode LX) we have an FPGA on the PCI bus that
currently only behaves as a PCI Target without burst mode.  Rather than
convert the FPGA design to a PCI Initiator with DMA, we are hoping to
make some minor changes to support burst reads from the FPGA.

However, while testing an FPGA design that should support burst reads we
noticed with a logic analyser that the Geode LX continues to only do
single target transfers.

Does anyone have any suggestions for what we could try to find out
what's going on?  Are there some MSRs that need to be set to enable
burst mode?

Regards,
Nathan