[coreboot] DL145 G1 with dual dualcore CPU using coreboot ?
Oskar Enoksson
enok at lysator.liu.se
Fri Sep 23 01:45:09 CEST 2011
On 09/22/2011 07:45 PM, Oskar Enoksson wrote:
> On 08/20/2010 10:39 PM, Myles Watson wrote:
>>> Attached is a cleaned-up patch. Thanks to Myles and others for
>>> excellent
>>> help and support. I hope someone finds the result useful.
>> Rev 5723.
>>
>> Thanks for contributing!
>> Myles
> Hi. One year after contributing the port to HP DL145 G1 motherboard
> code I decided to see if I could improve it a little. However, now I
> can't make it work. I still have my compiled rom image from August
> 2010 (and it works fine) but when I try to compile a new image I get
> all kinds of problems.
>
> First I checked out and compiled the latest git-version of coreboot.
> The result: no output whatsoever on the serial console. Something is
> very broken and there is no clue.
>
> Checking out the version just after my commit 2010-08-20 compiles and
> seems to boot, but depending on how much debugging messages I choose
> in "make menuconfig" I get different problems. Sometimes one of my two
> CPU's will not initialize. Sometimes I just get unexplicable lockups.
> More debugging messages seems to make it more stable.
>
> Since I believe I tried exactly the same sourcecode as I did
> successfully use one year ago I suspect a bug in my toolchain. I use
> gcc 4.5.1 and binutils 2.21. I think I used an older version last year.
>
> Question1: is there any particular version of gcc/binutils that is
> recommended with coreboot? Any versions one should avoid?
>
> Question2: is there any revision of coreboot after 2010-08-20 that is
> recommended to work well on amdk8 platforms?
Update: moving forward a few days from 2010-08-20 made the
debug-message-dependent lockup behaviour go away.
As for the "dead" behaviour in recent versions I bisected my way down to
commit 1f7d3c5672ec90f8d71907b1a07c8a87fa461047 (svn 6124). That commit
adds "TINY_BOOTBLOCK support" to AMD-8111 southbridge. I understand
that this commit splits up things into a "romstage" and "coreboot_ram".
But what is going wrong, and what should I do? All hints appreciated.
Thanks.
More information about the coreboot
mailing list