[coreboot] Patch set updated for coreboot: eb9d043 rs780: hide unused gfx ports and gpp ports
Kerry Sheh (shekairui@gmail.com)
gerrit at coreboot.org
Wed Sep 14 03:45:44 CEST 2011
Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/206
-gerrit
commit eb9d043e335aac286fd564ae01afca35d4cc9712
Author: Kerry Sheh <shekairui at gmail.com>
Date: Wed Sep 14 10:04:19 2011 +0800
rs780: hide unused gfx ports and gpp ports
Hide the unused gfx ports and gpp ports if they are not configured as hotplug.
lspci -vvv will get more accurate information under Linux,
tested on avalue/eax-785e.
Change-Id: Iaabfd362a0a01f21d0f49aa2bd2d26f9259013fb
Signed-off-by: Kerry Sheh <kerry.she at amd.com>
Signed-off-by: Kerry Sheh <shekairui at gmail.com>
---
src/southbridge/amd/rs780/gfx.c | 2 ++
src/southbridge/amd/rs780/pcie.c | 13 +++++++++++++
src/southbridge/amd/rs780/rs780.c | 5 ++++-
src/southbridge/amd/rs780/rs780.h | 1 +
4 files changed, 20 insertions(+), 1 deletions(-)
diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c
index 9262bb9..3c06d44 100644
--- a/src/southbridge/amd/rs780/gfx.c
+++ b/src/southbridge/amd/rs780/gfx.c
@@ -1009,6 +1009,7 @@ static void single_port_configuration(device_t nb_dev, device_t dev)
set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 3, 1 << 3);
}
} else { /* step 13.b Link Training was successful */
+ AtiPcieCfg.PortDetect |= 1 << 2; /* Port 2 */
set_pcie_enable_bits(dev, 0xA2, 0xFF, 0x1);
reg32 = nbpcie_p_read_index(dev, 0x29);
width = reg32 & 0xFF;
@@ -1064,6 +1065,7 @@ static void dual_port_configuration(device_t nb_dev, device_t dev)
set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, 1 << dev_ind);
} else { /* step 16.b Link Training was successful */
+ AtiPcieCfg.PortDetect |= 1 << dev_ind;
reg32 = nbpcie_p_read_index(dev, 0xa2);
width = (reg32 >> 4) & 0x7;
printk(BIOS_DEBUG, "GFX LC_LINK_WIDTH = 0x%x.\n", width);
diff --git a/src/southbridge/amd/rs780/pcie.c b/src/southbridge/amd/rs780/pcie.c
index 9cbd832..5e2d985 100644
--- a/src/southbridge/amd/rs780/pcie.c
+++ b/src/southbridge/amd/rs780/pcie.c
@@ -390,3 +390,16 @@ void config_gpp_core(device_t nb_dev, device_t sb_dev)
switching_gpp_configurations(nb_dev, sb_dev);
ValidatePortEn(nb_dev);
}
+
+/**
+ * Hide unused Gpp port
+ */
+void pcie_hide_unused_ports(device_t nb_dev)
+{
+ u16 hide = 0x6FC; /* skip port 0, 1, 8 */
+
+ hide &= ~(AtiPcieCfg.PortDetect | AtiPcieCfg.PortHp);
+ printk(BIOS_INFO, "rs780 unused GPP ports bitmap=0x%03x, force disabled\n", hide);
+ set_nbmisc_enable_bits(nb_dev, 0x0C, 0xFC, (hide & 0xFC)); /* bridge 2-7 */
+ set_nbmisc_enable_bits(nb_dev, 0x0C, 0x30000, ((hide >> 9) & 0x3) << 16); /* bridge 9-a */
+}
diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c
index d8f1be3..b8c7d04 100644
--- a/src/southbridge/amd/rs780/rs780.c
+++ b/src/southbridge/amd/rs780/rs780.c
@@ -362,7 +362,10 @@ void rs780_enable(device_t dev)
if (dev->enabled)
rs780_gpp_sb_init(nb_dev, dev, dev_ind);
- if (dev_ind == 10) disable_pcie_bar3(nb_dev);
+ if (dev_ind == 10) {
+ disable_pcie_bar3(nb_dev);
+ pcie_hide_unused_ports(nb_dev);
+ }
break;
default:
printk(BIOS_DEBUG, "unknown dev: %s\n", dev_path(dev));
diff --git a/src/southbridge/amd/rs780/rs780.h b/src/southbridge/amd/rs780/rs780.h
index aba3e69..5b8d251 100644
--- a/src/southbridge/amd/rs780/rs780.h
+++ b/src/southbridge/amd/rs780/rs780.h
@@ -213,4 +213,5 @@ u32 extractbits(u32 source, int lsb, int msb);
int cpuidFamily(void);
int is_family0Fh(void);
int is_family10h(void);
+void pcie_hide_unused_ports(device_t nb_dev);
#endif /* RS780_H */
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