[coreboot] New patch to review for coreboot: 7c7d871 Get rid of AUTO_XIP_ROM_BASE
Patrick Georgi (patrick@georgi-clan.de)
gerrit at coreboot.org
Fri Oct 28 20:32:24 CEST 2011
Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/348
-gerrit
commit 7c7d87182feb78cb2bc02fb3558bef56a41682c9
Author: Patrick Georgi <patrick at georgi-clan.de>
Date: Fri Oct 28 20:28:03 2011 +0200
Get rid of AUTO_XIP_ROM_BASE
That value is now generated from a code address and CONFIG_XIP_ROM_SIZE.
This works as MTRRs are fully specified by their size and any address
within the range.
Change-Id: Id35d34eaf3be37f59cd2a968e3327d333ba71a34
Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
src/arch/x86/Makefile.bootblock.inc | 4 ++--
src/cpu/amd/car/cache_as_ram.inc | 14 ++++----------
src/cpu/intel/car/cache_as_ram.inc | 12 +++---------
src/cpu/intel/model_106cx/cache_as_ram.inc | 11 +++--------
src/cpu/intel/model_6ex/cache_as_ram.inc | 11 +++--------
src/cpu/intel/model_6fx/cache_as_ram.inc | 11 +++--------
src/cpu/via/car/cache_as_ram.inc | 26 +++++++++++++++-----------
src/cpu/x86/mtrr/earlymtrr.c | 7 ++++++-
src/include/cpu/x86/mtrr.h | 12 ------------
9 files changed, 39 insertions(+), 69 deletions(-)
diff --git a/src/arch/x86/Makefile.bootblock.inc b/src/arch/x86/Makefile.bootblock.inc
index 806afea..9787032 100644
--- a/src/arch/x86/Makefile.bootblock.inc
+++ b/src/arch/x86/Makefile.bootblock.inc
@@ -76,13 +76,13 @@ $(obj)/bootblock.elf: $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.o $(obj)/bootbl
# Build the romstage
$(obj)/coreboot.romstage: $(obj)/coreboot.pre1 $$(romstage-objs) $(obj)/romstage/ldscript.ld
@printf " LINK $(subst $(obj)/,,$(@))\n"
- printf "CONFIG_ROMBASE = 0x0;\nAUTO_XIP_ROM_BASE = 0x0;\n" > $(obj)/location.ld
+ printf "CONFIG_ROMBASE = 0x0;\n" > $(obj)/location.ld
$(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/ldscript.ld $(romstage-objs)
$(OBJCOPY) -O binary $(obj)/romstage.elf $(obj)/romstage.bin
printf "CONFIG_ROMBASE = 0x" > $(obj)/location.ld
$(CBFSTOOL) $(obj)/coreboot.pre1 locate $(obj)/romstage.bin $(CONFIG_CBFS_PREFIX)/romstage $(CONFIG_XIP_ROM_SIZE) > $(obj)/location.txt
cat $(obj)/location.txt >> $(obj)/location.ld
- printf ';\nAUTO_XIP_ROM_BASE = CONFIG_ROMBASE & ~(CONFIG_XIP_ROM_SIZE - 1);\n' >> $(obj)/location.ld
+ printf ';\n' >> $(obj)/location.ld
$(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/ldscript.ld $(romstage-objs)
$(NM) -n $(obj)/romstage.elf | sort > $(obj)/romstage.map
$(OBJCOPY) --only-keep-debug $(obj)/romstage.elf $(obj)/romstage.debug
diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index 4899296..9d2b400 100644
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -281,24 +281,18 @@ clear_fixed_var_mtrr_out:
#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
-#if CONFIG_TINY_BOOTBLOCK
-#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
-#else
-#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
-#endif
-
/* Enable write base caching so we can do execute in place (XIP)
* on the flash ROM.
*/
movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx
/*
- * IMPORTANT: The two lines below can _not_ be written like this:
- * movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRPROT), %eax
+ * IMPORTANT: The following calculation _must_ be done at runtime. See
* http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/
- movl $REAL_XIP_ROM_BASE, %eax
- orl $MTRR_TYPE_WRPROT, %eax
+ movl copy_and_run, %eax
+ andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
+ orl $MTRR_TYPE_WRBACK, %eax
wrmsr
movl $MTRRphysMask_MSR(1), %ecx
diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc
index 2310d7d..4ad2fce 100644
--- a/src/cpu/intel/car/cache_as_ram.inc
+++ b/src/cpu/intel/car/cache_as_ram.inc
@@ -231,12 +231,6 @@ clear_fixed_var_mtrr_out:
#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
-#if CONFIG_TINY_BOOTBLOCK
-#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
-#else
-#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
-#endif
-
/*
* Enable write base caching so we can do execute in place (XIP)
* on the flash ROM.
@@ -244,11 +238,11 @@ clear_fixed_var_mtrr_out:
movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx
/*
- * IMPORTANT: The two lines below can _not_ be written like this:
- * movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+ * IMPORTANT: The following calculation _must_ be done at runtime. See
* http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/
- movl $REAL_XIP_ROM_BASE, %eax
+ movl copy_and_run, %eax
+ andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
orl $MTRR_TYPE_WRBACK, %eax
wrmsr
diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc
index da14db2..b45599a 100644
--- a/src/cpu/intel/model_106cx/cache_as_ram.inc
+++ b/src/cpu/intel/model_106cx/cache_as_ram.inc
@@ -102,17 +102,12 @@ clear_mtrrs:
/* Enable cache for our code in Flash because we do XIP here */
movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx
-#if CONFIG_TINY_BOOTBLOCK
-#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
-#else
-#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
-#endif
/*
- * IMPORTANT: The two lines below can _not_ be written like this:
- * movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+ * IMPORTANT: The following calculation _must_ be done at runtime. See
* http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/
- movl $REAL_XIP_ROM_BASE, %eax
+ movl copy_and_run, %eax
+ andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
orl $MTRR_TYPE_WRBACK, %eax
wrmsr
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index 02de5ab..fa35fc9 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -102,17 +102,12 @@ clear_mtrrs:
/* Enable cache for our code in Flash because we do XIP here */
movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx
-#if CONFIG_TINY_BOOTBLOCK
-#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
-#else
-#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
-#endif
/*
- * IMPORTANT: The two lines below can _not_ be written like this:
- * movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+ * IMPORTANT: The following calculation _must_ be done at runtime. See
* http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/
- movl $REAL_XIP_ROM_BASE, %eax
+ movl copy_and_run, %eax
+ andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
orl $MTRR_TYPE_WRBACK, %eax
wrmsr
diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc
index 2f13d35..a869011 100644
--- a/src/cpu/intel/model_6fx/cache_as_ram.inc
+++ b/src/cpu/intel/model_6fx/cache_as_ram.inc
@@ -109,17 +109,12 @@ clear_mtrrs:
/* Enable cache for our code in Flash because we do XIP here */
movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx
-#if CONFIG_TINY_BOOTBLOCK
-#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
-#else
-#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
-#endif
/*
- * IMPORTANT: The two lines below can _not_ be written like this:
- * movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+ * IMPORTANT: The following calculation _must_ be done at runtime. See
* http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/
- movl $REAL_XIP_ROM_BASE, %eax
+ movl copy_and_run, %eax
+ andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
orl $MTRR_TYPE_WRBACK, %eax
wrmsr
diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc
index 20b3220..d0c43c9 100644
--- a/src/cpu/via/car/cache_as_ram.inc
+++ b/src/cpu/via/car/cache_as_ram.inc
@@ -110,12 +110,6 @@ clear_fixed_var_mtrr_out:
movl $(~(CacheSize - 1) | MTRRphysMaskValid), %eax
wrmsr
-#if CONFIG_TINY_BOOTBLOCK
-#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
-#else
-#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
-#endif
-
/*
* Enable write base caching so we can do execute in place (XIP)
* on the flash ROM.
@@ -123,11 +117,11 @@ clear_fixed_var_mtrr_out:
movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx
/*
- * IMPORTANT: The two lines below can _not_ be written like this:
- * movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+ * IMPORTANT: The following calculation _must_ be done at runtime. See
* http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/
- movl $REAL_XIP_ROM_BASE, %eax
+ movl copy_and_run, %eax
+ andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
orl $MTRR_TYPE_WRBACK, %eax
wrmsr
@@ -168,7 +162,12 @@ clear_fixed_var_mtrr_out:
rep stosl
#ifdef CARTEST
- movl REAL_XIP_ROM_BASE, %esi
+ /*
+ * IMPORTANT: The following calculation _must_ be done at runtime. See
+ * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
+ */
+ movl copy_and_run, %esi
+ andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %ei
movl %esi, %edi
movl $(CONFIG_XIP_ROM_SIZE >> 2), %ecx
rep lodsl
@@ -244,7 +243,12 @@ testok:
/* Cache XIP_ROM_BASE-SIZE to speedup coreboot code. */
movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx
- movl $REAL_XIP_ROM_BASE, %eax
+ /*
+ * IMPORTANT: The following calculation _must_ be done at runtime. See
+ * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
+ */
+ movl copy_and_run, %eax
+ andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
orl $MTRR_TYPE_WRBACK, %eax
wrmsr
diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c
index dcfcccd..f8119d3 100644
--- a/src/cpu/x86/mtrr/earlymtrr.c
+++ b/src/cpu/x86/mtrr/earlymtrr.c
@@ -29,6 +29,8 @@ static void cache_lbmem(int type)
enable_cache();
}
+const int addr_det = 0;
+
/* the fixed and variable MTTRs are power-up with random values,
* clear them to MTRR_TYPE_UNCACHEABLE for safty.
*/
@@ -52,8 +54,11 @@ static void do_early_mtrr_init(const unsigned long *mtrr_msrs)
#if defined(CONFIG_XIP_ROM_SIZE)
/* enable write through caching so we can do execute in place
* on the flash rom.
+ * Determine address by calculating the XIP_ROM_SIZE sized area with
+ * XIP_ROM_SIZE alignment that contains the global variable defined above;
*/
- set_var_mtrr(1, REAL_XIP_ROM_BASE, CONFIG_XIP_ROM_SIZE, MTRR_TYPE_WRBACK);
+ unsigned long f = (unsigned long)&addr_det & ~(CONFIG_XIP_ROM_SIZE - 1);
+ set_var_mtrr(1, f, CONFIG_XIP_ROM_SIZE, MTRR_TYPE_WRBACK);
#endif
/* Set the default memory type and enable fixed and variable MTRRs
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index 44a2223..dc238e7 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -67,16 +67,4 @@ void x86_setup_fixed_mtrrs(void);
# error "CONFIG_RAMTOP must be a power of 2"
#endif
-#if !defined (__ASSEMBLER__)
-#if defined(CONFIG_XIP_ROM_SIZE)
-# if CONFIG_TINY_BOOTBLOCK
- extern unsigned long AUTO_XIP_ROM_BASE;
-# define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
-# else
-# define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
-# endif
-#endif
-
-#endif
-
#endif /* CPU_X86_MTRR_H */
More information about the coreboot
mailing list