[coreboot] Patch set updated for coreboot: 8ae1d47 T60: add _CST table

Sven Schnelle (svens@stackframe.org) gerrit at coreboot.org
Tue Oct 25 20:15:49 CEST 2011


Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/322

-gerrit

commit 8ae1d4744e20ee90d4118f20ba5ee2a93bf0b6d1
Author: Sven Schnelle <svens at stackframe.org>
Date:   Sat Oct 22 13:41:28 2011 +0200

    T60: add _CST table
    
    Used by power management code to enable Cx powersaving modes.
    
    Change-Id: I02c6b10762245bc48f21a341286236e203421de0
    Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/mainboard/lenovo/t60/mainboard.c |   13 +++++++++++++
 1 files changed, 13 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/lenovo/t60/mainboard.c b/src/mainboard/lenovo/t60/mainboard.c
index d4f260d..19ac221 100644
--- a/src/mainboard/lenovo/t60/mainboard.c
+++ b/src/mainboard/lenovo/t60/mainboard.c
@@ -35,6 +35,19 @@
 #include <ec/lenovo/h8/h8.h>
 #include <northbridge/intel/i945/i945.h>
 #include <pc80/mc146818rtc.h>
+#include <arch/x86/include/arch/acpigen.h>
+
+static struct cst_entry cst_entries[] = {
+	{ 0x7f, 1, 2, 0, 1, 1, 1, 1000 },
+	{ 0x01, 8, 0, 0, DEFAULT_PMBASE + LV2, 2, 1, 500 },
+	{ 0x01, 8, 0, 0, DEFAULT_PMBASE + LV3, 2, 17, 250 },
+};
+
+int get_cst_entries(struct cst_entry **entries)
+{
+	*entries = cst_entries;
+	return ARRAY_SIZE(cst_entries);
+}
 
 static void mainboard_enable(device_t dev)
 {




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