[coreboot] Patch set updated for coreboot: 96d3f10 i82801gx: Add setting for C4onC3 mode

[Sven Schnelle (svens@stackframe.org)]

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/329

-gerrit

commit 96d3f107bdc76252cbe3e22c7aef59c89f3ab988
Author: Sven Schnelle <svens at stackframe.org>
Date:   Sun Oct 23 16:35:01 2011 +0200

    i82801gx: Add setting for C4onC3 mode
    
    If this bit is set, ich7 will enter C4 mode if possible instead of
    C3. See ich7 specification (LPC controller, Power management control
    registers) for more details.
    
    Change-Id: I352cccdbc51ff6269f153a4542c7ee1df0c01d22
    Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/southbridge/intel/i82801gx/chip.h |    2 ++
 src/southbridge/intel/i82801gx/lpc.c  |    4 ++++
 2 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h
index 4aea26e..b775d39 100644
--- a/src/southbridge/intel/i82801gx/chip.h
+++ b/src/southbridge/intel/i82801gx/chip.h
@@ -68,6 +68,8 @@ struct southbridge_intel_i82801gx_config {
 	uint32_t ide_enable_primary;
 	uint32_t ide_enable_secondary;
 	uint32_t sata_ahci;
+
+	int c4onc3_enable:1;
 };
 
 extern struct chip_operations southbridge_intel_i82801gx_ops;
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index ab3c915..c6b76d3 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -243,6 +243,10 @@ static void i82801gx_power_options(device_t dev)
 	reg16 |= (1 << 2);	// CLKRUN_EN - Mobile/Ultra only
 	reg16 |= (1 << 3);	// Speedstep Enable - Mobile/Ultra only
 	reg16 |= (1 << 5);	// CPUSLP_EN Desktop only
+
+	if (config->c4onc3_enable)
+		reg16 |= (1 << 7);
+
 	// another laptop wants this?
 	// reg16 &= ~(1 << 10);	// BIOS_PCI_EXP_EN - Desktop/Mobile only
 	reg16 |= (1 << 10);	// BIOS_PCI_EXP_EN - Desktop/Mobile only