[coreboot] New patch to review for coreboot: 6b91039 Add bootstrap to select loaded ramstage

[Kyösti Mälkki (kyosti.malkki@gmail.com)]

Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/304

-gerrit

commit 6b910392411668b395536da4646d620f3efd2fc7
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Thu Oct 20 21:06:14 2011 +0300

    Add bootstrap to select loaded ramstage
    
    Just before loading ramstage, read the console serial port
    pin (DCD). If it is high, select alternative prefix for ramstage.
    
    Suggested use: During ramstage development, never overwrite
    a stable combination of romstage, ramstage and payload on a flash
    device. Instead, place the ramstage to test under the alternative
    prefix.
    
    Change-Id: Ib8b6984ddd886cd21638880c6f43dd90d078c844
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/Kconfig                         |   13 +++++++++++++
 src/arch/x86/lib/cbfs_and_run.c     |   14 ++++++++++++++
 src/arch/x86/lib/romstage_console.c |    7 +++++++
 src/console/Kconfig                 |    9 +++++++++
 src/include/console/console.h       |    1 +
 src/include/uart8250.h              |    1 +
 src/lib/uart8250.c                  |    5 +++++
 7 files changed, 50 insertions(+), 0 deletions(-)

diff --git a/src/Kconfig b/src/Kconfig
index 525d452..a224cdf 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -46,6 +46,19 @@ config CBFS_PREFIX
 	  Select the prefix to all files put into the image. It's "fallback"
 	  by default, "normal" is a common alternative.
 
+config DUAL_RAMSTAGE
+	bool
+	default y if TTYS0_DCD_HOOK
+	default n
+
+config CBFS_ALT_PREFIX
+       string "Alternative CBFS prefix to use"
+       depends on DUAL_RAMSTAGE
+       default "normal"
+       help
+          Select the prefix for an alternative coreboot RAM stage.
+          You need some hardware bootstrap to make this choice at boottime.
+
 choice
 	prompt "Compiler"
 	default COMPILER_GCC
diff --git a/src/arch/x86/lib/cbfs_and_run.c b/src/arch/x86/lib/cbfs_and_run.c
index ad36ddc..b4e6883 100644
--- a/src/arch/x86/lib/cbfs_and_run.c
+++ b/src/arch/x86/lib/cbfs_and_run.c
@@ -40,11 +40,25 @@ static void cbfs_and_run_core(const char *filename, unsigned ebp)
 
 void __attribute__((regparm(0))) copy_and_run(unsigned cpu_reset)
 {
+#if CONFIG_DUAL_RAMSTAGE
+	int bootstrap = 0;
+#endif
 	// FIXME fix input parameters instead normalizing them here.
 	if (cpu_reset == 1) cpu_reset = -1;
 	else cpu_reset = 0;
 
+	/* Go altenative way, if any bootstrap returns non-zero */
+#if CONFIG_TTYS0_DCD_HOOK
+	bootstrap += !!console_dcd();
+#endif
+#if CONFIG_DUAL_RAMSTAGE
+	if (! bootstrap)
+		cbfs_and_run_core(CONFIG_CBFS_PREFIX "/coreboot_ram", cpu_reset);
+	else
+		cbfs_and_run_core(CONFIG_CBFS_ALT_PREFIX "/coreboot_ram", cpu_reset);
+#else
 	cbfs_and_run_core(CONFIG_CBFS_PREFIX "/coreboot_ram", cpu_reset);
+#endif
 }
 
 #if CONFIG_AP_CODE_IN_CAR == 1
diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c
index 8adb3ba..587e331 100644
--- a/src/arch/x86/lib/romstage_console.c
+++ b/src/arch/x86/lib/romstage_console.c
@@ -61,6 +61,13 @@ static void console_tx_flush(void)
 #endif
 }
 
+#if CONFIG_TTYS0_DCD_HOOK
+int console_dcd(void)
+{
+	return uart8250_dcd(CONFIG_TTYS0_BASE);
+}
+#endif
+
 int do_printk(int msg_level, const char *fmt, ...)
 {
 	va_list args;
diff --git a/src/console/Kconfig b/src/console/Kconfig
index 02244d7..ea16c0c 100644
--- a/src/console/Kconfig
+++ b/src/console/Kconfig
@@ -91,6 +91,15 @@ config TTYS0_LCS
 	default 3
 	depends on CONSOLE_SERIAL8250 || CONSOLE_SERIAL8250MEM
 
+config TTYS0_DCD_HOOK
+	bool "DCD line is bootstrap to alternative ramstage"
+	default n
+	depends on CONSOLE_SERIAL8250
+	help
+	  Status of DCD line on the selected serial debug console
+	  port is read at boot-time, and is used to choose from
+	  two ramstage prefixes.
+
 # Use "select HAVE_USBDEBUG" on southbridges which have Debug Port code.
 config HAVE_USBDEBUG
 	def_bool n
diff --git a/src/include/console/console.h b/src/include/console/console.h
index 8283f66..f37e7b5 100644
--- a/src/include/console/console.h
+++ b/src/include/console/console.h
@@ -62,6 +62,7 @@ extern int console_loglevel;
 
 #ifndef __ROMCC__
 void console_init(void);
+int console_dcd(void);
 void post_code(u8 value);
 void __attribute__ ((noreturn)) die(const char *msg);
 int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3)));
diff --git a/src/include/uart8250.h b/src/include/uart8250.h
index 4a02179..fe49161 100644
--- a/src/include/uart8250.h
+++ b/src/include/uart8250.h
@@ -138,6 +138,7 @@ void uart8250_tx_flush(unsigned base_port);
  */
 void uart8250_init(unsigned base_port, unsigned divisor);
 void uart_init(void);
+int uart8250_dcd(unsigned base_port);
 
 /* and the same for memory mapped uarts */
 unsigned char uart8250_mem_rx_byte(unsigned base_port);
diff --git a/src/lib/uart8250.c b/src/lib/uart8250.c
index b224671..3221a94 100644
--- a/src/lib/uart8250.c
+++ b/src/lib/uart8250.c
@@ -62,6 +62,11 @@ int uart8250_can_rx_byte(unsigned base_port)
 	return inb(base_port + UART_LSR) & UART_LSR_DR;
 }
 
+int uart8250_dcd(unsigned base_port)
+{
+	return inb(base_port + UART_MSR) & UART_MSR_DCD;
+}
+
 unsigned char uart8250_rx_byte(unsigned base_port)
 {
 	while(!uart8250_can_rx_byte(base_port))